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Nothing was pasted from the Clipboard.Failed obtaining an IFF Handle.Error opening `Clipboard, unit 0`.`OpenIFF` for write failed. NbEFothing was pasted to the Clipboard.Error writing `FTXT` to IFF Stream. Nothing was pasted to the Clipboard.Error writing `CHRS` to IFF Stream. Nothing was pasted to the Clipboard.Failed to write to ClipboardError closing `CHRS` Chunk. Nothing was pasted to the Clipboard.Error closing `FTXT` Chunk. Nothing was pasted to the Clipboard.There was nothing to past from the Clipboard. Will past locally stored data instead.Failed to install ExitHandler for ParseIFF. Will past locally bF`pstored data instead.Not enough memory to past data from Clipboard. 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YDUg -Vj6P T z d:{ Cf:v)Ld7Zr3g@`|0^7Tm*<N`s%QrWorkspace Memory FullAddress Register Byte/LogicAddress Register ExpectedComma Expected Data Register ExpectedDouble SymbolUnexpected End of FileUser made FAILIllegal CommandIllegal Address SizeIllegal Operb8@(6andIllegal OperatorIllegal Operator in BSS AreaIllegal OrderIllegal Register SizeIllegal Section TypeIllegal SizeIllegal MACRO DefinitionImmediate Operand ExpectedInclude JamMACRO OverflowInvalid Addressing ModeLOAD without ORGMissing QuoteConditional OverflowNo Operand Space AllowedNot a Constant/LabelNot in MACROOut of Range 0 BitOut of Range 3 BitOut of Range 4 BitOut of Range 5 BitOut of Range 6 BitOut of Range 7 BitOut of Range 8 BitOut of Range 16 BitRb9Фelative Mode ErrorReserved WordClosing Parenthesis ExpectedSECTION OverflowString ExpectedUndefined SymbolRegister ExpectedWord at ODD AddressNot Local AreaCode moved during PASS 2Bcc.B Out of Range in MACROOut of Range (20 to 100)Out of Range (60 to 132)Include OverflowLinker LimitationRepeat OverflowNot in Repeat AreaDouble DefinitionRelocation made to EMPTY SectionFile Error No Files No Object No File SpacePrinter Device Missing Not doneIllegal Path Ilb:iulegal DeviceWrite ProtectedNo disk in DriveIllegal Option !!REM without EREMTEXT without ETEXTIllegal Xn SCALE Size. Only nothing, 1, 2, 4 or 8 allowedField Offset Expected: {OFFSET:width}Missing BraceColon ExpectedMissing BracketFPU needed for Operation !!To Many Watchpoints (maximal 8)Illegal Source, not Activated !!No Valid Memory Directory PresentAUTO Command Overflow (more than 256 characters)End should be Higher than Start !Warning, Value Signed Extended to Lonb; čgwordIllegal Source NumberIncluding Empty Source ?Include Source JamUnknown Conversion Mode: should be RB or RNUnknown CMAP Place: should be (B)EFORE,(A)FTER or (N)ONEUnknown CMAP Mode: should be AGA or ECSTrying to Include NON IFF FileIFF File is Not a ILBM FileCan't handle a BODY before BMHD Chunk>> Warning << Value Sign Extended, Resulting in Negative >> Warning << 68010++ Command Used >> Warning << 68020++ Command Used >> Warning << 68030++ Command Used >> Warning <b> Warning << 68020++ Addressing Mode Used >> Warning << 68010 Specific Command Used >> Warning << 68020 Specific Command Used >> Warning << 68030 Specific Command Used >> Warning << 68040 Specific Command Used >> Warning << 68060 Specific Command Used >> Warning << MOVEP not supported by the 68060 >> Warning << 68881/68882 Command Used >> Warning << 68030/68851 Command Used >> Warning << 68851 Specific Command Used >> Warninb=Vzg << PFLUSHA Assembled with 68030/68851 >> Warning << PFLUSHA Assembled with 68040/68060 >> Warning << 68020/030/040 Specific Command Used >> Warning << 68020/030 Specific Command Used >> Warning << Relative Offset NOT Allowed for Outerdisplacement >> WARNING << Pointer to Error Table was to low !!!! A1 was $00000000. While table started at: $00000000 !!!! >> YEAH !! << Error Pointer was Restored. Only .L allowed when moving FPU Control Registers !!Illegal Size for Data b>s6Register: should be B, W, L or SBcc.W Out of Range in MACROFloating Point Register Expected** This is not an ASM-One Project File Offset+Width can't be out of 32 Bit RangeIllegal CMAP Mode Error: expecting 12, 24, CE or CAIllegal Color Offset (Bank) SpecifiedIFF Color(s) Out of RangeTo Many ErrorsInvalid Function Code: only SFC, DFC, Data Register or Immediate AllowedInvalid Address Error: d0 = $00000000, d1 = $00000000, d2 = $00000000, d3 = $00000000 d4 = $00000000, d5 = $b?&ND00000000, d6 = $00000000, d7 = $00000000Address Register Indirect Mode Expected, for Return Address RegisterAddress Register Direct Mode Expected, for Return Address RegisterLevel Out of 3 Bit RangeMask Out of 3 Bit RangeMask Out of 4 Bit RangeFunction Code Out of 3 Bit RangeFunction Code Out of 4 Bit RangeInsuficient Memory to change SourceMMU Register Expected as 1st OperandMMU Register Expected as 2nd OperandInvalid MMU Register as 1st Operand: CAL, VAL or SCC Expectedb@Invalid MMU Register as 2nd Operand: CAL, VAL or SCC ExpectedOut of Range 32 Bit** Missing START address or Label !! ** Missing END address or Label !! Incorrect Index Register Specified. Only An, Dn or SP allowedPC/ZPC can't be used as Index Register. Only An, Dn or SP allowedWe haven't come up with a nice text for this error Error !!!!The use of ZPC is not allowed in this addressing mode !!Field Width Expected: {offset:WIDTH}Field Width can't be ZEROIllegal Addressing ModbA|Xe used as Source OperandIllegal Addressing Mode used as Destination OperandIllegal Register used as Source OperandIllegal Register used as Destination OperandNo Immediate Data allowed as OperandOnly Dy,Dx or -(Ay),-(Ax) Allowed !!Only WORD Size Allowed !!No Negative Value Allowed !!Only Data or Address Registers Allowed !!Illegal Register UsedUse .X for FPU Data Registers, or .L for FPU Control RegistersFPU Data Register (single or list) Expected !!FPCR, FPSR, FPIAR expecbB~o%ted (or a combination of them)Only the FPIAR is Allowed when An is the Source or Destination !!Only the FPCR, FPSR or FPIAR is Allowed !!FPU Data Register (FPn) Expected !!Invalid OPT operand(s) specified !!.P not allowed when using FSMOVE or FDMOVE !!General AltiVec Register ExpectedGeneral PPC Register ExpectedGeneral PPC Floatingpoint Register ExpectedShift Amount in Bytes Expected (SHB)Unsigned 16-bit Integer Expected (UIMM)Signed 16-bit Integer Expected (SIMM)Data StbCJMream ID Expected (STRM)Conditional Branch Condition Bits Expected (BO)Expected which CR bit to be used as Condition (BI)Expected 14-bit Branch Displacement (BD)CR-bit ExpectedRc-bit ExpectedOE-bit ExpectedSpecial Purpose Register Expected16-Bits Displacement ExpectedCR Field Mask Expected (CRM)FPSCR Field Mask Expected (FM)Shift Amount Expected (SH)32-Bit Mask Begin Expected (MB)32-Bit Mask End Expected (ME)Number of Bytes to Move Expected (NB)Expected One of the 16 SebDծgment Registers (SR)Out of Range 0 - 1Out of Range 0 - 3Out of Range 0 - 7Out of Range 0 - 15Out of Range 0 - 31Out of Range 0 - 63Out of Range 0 - 255Out of Range 16 bitOut of Range 24 bitNot 32-bit AllignedIllegal BOIllegal BIExpected LK-BitCould not Open Device...IO was Aborted...Command not Supported by Device...Not a Valid Lenght...Invalid Address (bad aligned or bad range)...Device opens OK, but it is Busy...Hardware Selftest Failed...Unknown IO Error... (ebE8l:rror: )A4 Debug : - @0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ[ABCDEFGHIJKLMNOPQRSTUVWXYZASM-One V1.49-RC2ASM-One's_PortENVARC:ASM-One.PrefS:REGSDATASorry, ASM-One V1.49-RC2 requires Kickstart 2.x or higher !! kkAAProjectOpen...OUse....bF~USave...SSave As...AExit Preferences QEditReset to DefaultsDLast Normal SavedLWorkbenchReqTools LibrarySave MarksSource .ASMUpdate CheckPrinter DumpWB to frontResident RegistersClipboard SupportSafetyClose WorkbenchParametersASCII OnlyDisassemblyShow SourceEnable/PermitLibcalls decRealtime debLine NumbersAuto IndentExtended ReqToolsCTRL up/downKeep xRTG ModePrefs:General ParametersMonitor / DebuggerEditorSaveUseCancelDefault Dir:BootbGudUpSource ExtensionSelect new screen modeAssemblerSaveUseCancelRescueLevel 7NumLockAuto AllocDebugList FilePagingHalt FileAll ErrorsProgress IndicatorProgress by LineLabel :UCase = LCase; CommentProcessor WarnCPUFPU Present68020++ Odd dataDS Clear68851 PresentNot enough memory to open preferences window ENVARC:ASM-One.pref saved ENVARC:ASM-One.pref {re}loaded bH#A  U f* q6 }B N [ [6 [ [*  [B      *  6  bIS&B N ( ` m 5} B N[N t%n n n v v~vxuEbJV Z Z xE!n  n n x x$ $x0 ,x< 4xH ?8 E8$ O 80 V 8< ` 8H k 8T bKG~  $ 0 < H T 8` ` W{ HcbL..-.-W-U.9999bM೯-9defgjDk  ln+prCstu( Please select prefered screenmodeASM-One - Environment PreferencesASM-One - Assembler PreferenbNjces #57I-0-6-<-B-H-N-T680006801068020680306804068060PPC C........ .".$.&.(.*.,...0.2.4.6.8.:.<.>.@.B.D.F.H.J.L.N.P.R.T.V.X.Z.\.^.`.b.dbOHj'''''( ((,(<(L(\(l(|(((((((() )1HAssembly Time: : : 000% Complete Line!#$%&()*+-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_abcdefghijklmnopqrstuvwxyz{|}~bPu0123456789ABCDEF0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ[ABCDEFGHIJKLMNOPQRSTUVWXYZ  bQ DA>Extend Labels with>Prefix (Y/N)>DIRECTORYNAME>Startup Parameters>K>BEG>END>DEST>DATA>AMPLITUDE>MULTIPLIER>HALF CORRECTION (Y/N)>ROUND CORRECTION (Y/N)>YOFFSET>SIZE (B/W/L)>AMOUNT>BREAKPOINT>RAM PTR>DISK PTR>LENGTH>Sure? S:REGSDATA File nbTaot Found, Aborting Not Enough Memory to Load S:REGSDATA, Aborting Could not Load IFF File Error Creating Directory Directory Created Sinus Created. Couldn't open mathffp.library Couldn't open mathtrans.library mathffp.librarymathtrans.librarySource NOT saved !! Continue? File already Exists !! Continue ?Exit or Restart (Y/N or R)? ONOFFEOP EOP Remove UNused Labels (Y/N)?Updating .. File Lost ?? Updating Anyway... Source not changed. No update needed !!bUC7) Sorting Reloc Area.. Writing Hunk Data.. Writing Hunk Length.. Memory Overflow !!!NL -- L7 -- RS--Mode : Reqtools.library NOT Found !!! Reqtools.library Disabled due to no Free Chip Memory !!! Not Enough Workmemory for Source !!! ** Break 1HPass 1.. 1HPass 2.. Page Of 1HNo Errors 1HErrors Occured !! 1HSource Checked 1HReAssembling.. Option O: Optimizing.. NOT Equal Areas** Warning: Searching.. Not Found Searching.. bVNFound Branch Forced to Word SizeBranch Forced to Long SizeFPCR= FPIAR=FPSR= BSUN= SNAN= OPERR= OVFL= UNFL= DZ= INEX2= INEX1= PRECISION= ROUNDING= N= Z= I= NAN= S= QU= IOP= OVFL= UNFL= DZ= INEX=VBR= FP0: FP4: D0: A0: SSP=USP=SR=T1--SI--PL=XNZVC PC=PC=01;061HFP0:02;061HFP1:03;061HFP2:04;061HFP3:05;061HFP4:06;061HFP5:07;061HFP6:08;061HFP7:09;069HD0: 10;069HD1: 11;069HD2: 12;069HD3: 13;069HD4: 14;069bWРHD5: 15;069HD6: 16;069HD7: 17;069HA0: 18;069HA1: 19;069HA2: 20;069HA3: 21;069HA4: 22;069HA5: 23;069HA6: 24;069HA7: 25;069HSSP=26;069HUSP=27;069HSR=PL=28;069HT1--SI--XNZVC29;069HPC =30;069HVBR=31;068HFPSR=01;061HFP0:02;061HFP1:03;061HFP2:04;061HFP3:05;061HFP4:06;061HFP5:07;061HFP6:08;061HFP7:01;069HD0: 02;069HD1: 03;069HD2: 04;069HD3: 05;069HD4: 06;069HD5: 07;069HD6: 08;069HD7: 09;069HA0: 10;069HA1: 11;069HA2bX.$t: 12;069HA3: 13;069HA4: 14;069HA5: 15;069HA6: 16;069HA7: 17;069HSSP=18;069HUSP=19;069HSR=PL=20;069HT1--SI--XNZVC21;069HPC =22;069HVBR=23;068HFPSR= Start End Total -------- -------- -------- Workspace : Source : Label Pointers : Label : Debug : Code : Reloc : IncMem : -------- -------- ASM-One Location Start End Total bYSz -------- -------- -------- 1st Code Section: 2nd Code Section: 1st Data Section: 2nd Data Section: BSS Data Section: --- Memory Directory --- -- Symbol Table -- bZ4 999;1HLine: Col: Bytes: Free: / ----- Time: : : Bytes Words Longwords Start : $xxxxxxxx End : $xxxxxxb[xx Size : Longwords Time : xx:xx:xx 999;1H DC.B DC.W DC.L INSERT_POINT Search for: Replace with: Jump to Line: No More Errors Found Error : Steps: Address: Watch: Add Conditional Breakpoint on : Compareson Value/Register : Condition Type: (0) < (1) <= (2) = (3) > (4) >= (5) <> : Condition Breakpoint Reached Mode NOT allowed in Conditional Breakpoint Address NOT Found !! End of Program Reached !! Watch type (A)scii (S)tring (H)ex (D)ecib\Dic-mal (B)inary (P)ointer: Pointer to (A)scii (S)tring (H)ex (D)ecimal (B)inary: Pointer type (1) DC.L (2) DC.W (3) DR.L (4) DR.W : Register: Replace (Y/N/L/G)? Jumping.. Jumping.. Done Search for: Jump to Line: b]pL Address: Steps: Register: b^ Add Conditional Breakpoint on : Compareson Value/Register : b_7 Watch: FILENAME> Replace wb`Vith: Buffer Full !!Done Uncomment Done Searching.. Top of Text.. Top of Text.. Done Bottom of Text.. Bottom of Text.. Done Create MACRO.. Mark Location and Press MACRO Buffer Full !!EXTERN;;topaz.fontconsole.devicetrackdisk.devicetimer.deviceASM-One V1.49-RC2 ba Raised At $ Accessing $ Type Instruction $ SSW: $ FSLW : $ALLOCATE Fast/Chip/Publ/Abs>ABSOLUTE Memory Addr.>ADD-WORKSPACE (Max.) KB>PRT:graphics.libraryintuition.librarydos.librarygadtools.libraryasl.libraryicon.libraryreqtools.libraryamigaguide.libraryiffparse.libraryutility.library  !"#$%+ -2(5:R,9 _ bb_ _&R"Rۀ _&S"SSearch from cursor position for what_Search|_Case dependant search|_AbortSearch and replaceSearchSearch for '' and replace it with _Replace|_AbortFound it !!, should it be replaced ?_Yes|_No|_Last|_Global|_AbortJump to which line number_Jump|_Abortbc\Select coloursASM-One V1.49-RC2 AmigaGuide handlerAGA AmigaGuide already actives:AGA.GuideASM-One V1.49-RC2 custom registers information (AGA)Unable to open amigaguide.libraryUnable to open the AGA.GuideSource .S ASM-One V1.49-RC2 PUTT^RS\L7ZNLXAA RLFXR PDLLFJPGHHPFAE:DBIL CB.SCWLNAI,L:DASSOAUL;CPIPLPSRRbd|'AUSMFWFPODDCUDEPLDKXMPSORDWFRTbeobfDK<DMU^fov~Read sourceWrite sourceRead binaryWrite binaryRead objectWrite objectWrite linkWrite blockDirect outputZap fileInsert sourceSelect preference file to loadSelect preference file to saveWrite ProjectRead Project()3[3[3[3[(#?.ASM|#?.S)#?.Pref#?.Aprj _\bg*F9 _\ _\9ASM-One V1.49-RC2 Warning !!About ASM-One V1.49-RC2....About to exit ASM-One !! Are you sure ??File already exists !! Are you sure ??Source 0 not saved yet ! Save changes, Continue or abort ?_Yes|_Restart|_No_Save|_Continue|_Abort_Overwrite|_Leave_Yes|_No_Ok|_Ok_Ok_OkThe RTG Mode has been disabled because you don't have KS/WS 3.x or higher !! bhR ASM-One V1.49-RC2 by T.F.A. ASM-One V1.49-RC2, based upon V1.48 Contact us for bugreports and/or ideas at Email : Boushh@TheFlameArrows.info - Boushh WWW : http://www.TheFlameArrows.info (C) 2008 by TFA -- - --+- -- - -+*>> ArTiSt'S WiTh An AtTiTuDe <<*+- - -- -+-- - -- New source, no name given yetCON:0/11/635/189/ASM-One V1.49-RC2 by T.F.A.CON:0/0/635/200/Dos command output wibijlndowExecution complete. Press return...No project startedNo sourceASM-One Project : Source #0 : Size : Source #1 : Size : Source #2 : Size : Source #3 : Size : Source #4 : Size : Source #bjy5 : Size : Source #6 : Size : Source #7 : Size : Source #8 : Size : Source #9 : Size : bk-Number of labels found: blabm_bn]bo[bpYbqWbrUbsSbtQbuUJ................................ !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~...............................................................................................................................................................................................................................................................................................................................................................bv`Sn.................................. !!0!N!l!!!!"" ">"\"z""""##.#L#j####$$$<$Z$x$$$$%%,%J%h%%%%%&&:&X&v&&&&' '*'H'f'')+$+,6,J,N,^,b,r,v,,,,,,,,,----- -$-(bw'-j-n-r-v-z-~--------------------------------... ................../// ///R RRpRxRRUXU~U[n[z[[[[\ )\Q)t.0aaa4afaaaala ja",m05ahJ,Yf$aBN`NnNN:la`a|Yaa a abx:Bahana`H,lV0<.9Yg0CUnp,lVN#5g#] l!@Nuaa`,lV y5B5NA ,lRNg#NuA ,yNg#NuA,lRN#Nu,lR"yNa"lo( yb{X,lRNNuava/ @r( x(!AE"I"h"&h(0(&4(SB6KTKrBB0@RAQPJQa"_`G""K$K F&fNuE"2<pPJQNuC$p$,xN#Nu"y,xNbNuCQp$,xN)@RNu"lR,xNbNuNa#"C3#|@ #l,xNNu,lJ"<P$<,lJN)@NfYANLNu,mNe NeHAh~ (fAfQL`0 Ch@mNe HNfXLAfQLNuAh~ Jg,"h (H,xN.LH~? Qb|ϪiLAfQNuaVNfv?N&Na050\@|mdNp:"l ,,xN.NN)l"yg 9P,xN.0 RfN:l.lNaNXC3,xN,lJ",NgN"N,yNbXOFA)H3fAPNkAd"< Pg("< Fg"< Cgr AgZ"</APNz"/,xN(vN8 _No8ft)@",xN:JgX`HAPNo8fF/APNzp?NNo8f$)@"_,xN4Jg)@Ѭ ld)H @)H)Hb}e)H)H)H)HNeNeraJNFAPNzp?NNo8f"g"l/,xN4"JgӬӬN\ l!|2Nu yU\tv4(6( WB9BJ9B"H@9@69Z gT@d@0E H@H @0E!H@@0E" 3UD3Uf3Uj3[\U"9@S@9@H9@H@(9@0H9@H9@iH@(9@ 0S@?p0,i9@ HAq`p0,ir2,iЁ!@r2pvJrFJ*@hf"b`^\ZV4   >TMTA(fTATMNuTATM1U hf* hf"1|`TATM1U`TATM1U(gJJFgUFgUFgUFgUFgUFgUFgJEgvSEbGQx gSEgjSEgjSEg`ZNu0(HJ@gfS@g`S@gS@gS@g:S@gS@g0NuPMPANu A NuTATM0X@1@1U Fo F m`@TATM Fo F m0g1@X@1@``TMTA Fo F m Fm Eg Eg0g1@X@1@`TMTA Fol F mfgJEg^ Egn0gL1@X@1@`TMTA Fo, F m&0g1@X@1@`TTT Fo F mgJEg Eg0g1@X@1@` Fg Fg`NuTATM:(gME Eg EfTMTA`XMXAbCC:(Eg Eg EfTMTA`XMXANuJFgbUFg^UFgZUFgVUFgRUFgPUFgRJEgHSEg\SEg@SEgBSEg8`4TATMJFg,UFg(UFg$UFg UFgUFgUFgJEgSEg&SEg SEg SEgNuTATMNu:(f:TATMNuXAXMNu\A\MNuJ-g ljRm -f\M\ANuAj g6 g. g g\`X0309J@gN:` lZ\fN:`a>B9oz A o r ozv AGof K0aUAfC g QNuGo{A^/ 0r@A0Hr@0Hr@0r@0Hr@0r@0Hr@0Hr@000rHA002YA02IA02@@0Y0A0H@0Abh^0(@1@CN0Jgr tcvzxqzxfpWJ-gpB ljRm -fpLfE RISAfE|` f|~E 9Bo|f0(HhF`0(F .ftC@ g"SARI gSARI gSARI Cf2tcAp.pW 9To|f hfpL` (gpLQp ga6g p,a(B9Z f,EfJ9ogoB9oAo{"  f|m"_NuT F HILSCCCSNEEQVCVSPLMIGELTGTLEF EQ OGT OGE OLT OLE OGL OR UN UEQ UGT UGE ULT ULE NE T SF SEQ GT GE LT LE b߰GL GLE NGLENGL NLE NLT NGE NGT SNE ST BS BC LS LC SS SC AS AC WS WC IS IC GS GC CS CC Jk":(<(9|n Ff.g(9|n` :( <(9|n Ff g9|nMHJ@j@{NZX@b*vh0n, : D * 4 &.  @ > .:F:<<VrNz Nu0(@ @nap,:(M``0( @g @g pB` pD`pIpCNuTM(f a,0( @gl @gv`fHz`,`TM(f abW,0( @g @ g ` Hz`,``TM(f&aR,0(J@f pTpCNu @g >` (a,`&TM(f0a,0(g @g b @ g h` ~J9Z0g ` 0(gHz( @g 6 @ g <` RJ9Z0ga X`a `,`TM0(H@J@fa `( @fa ` @n:Ea:(M`aP,anJhg,,#0(Ha8:(M(g ,`Nu(fNuTMNuTMHz(0(HJ@f a *,NuS@f a ",Nuf:(MEa::(M,Nu0(Ha,NuTMHz0(g:(MEa,:(MNuVALbE,NuTM0(H2AJAgSAg An @:a`aH` a z`a z,0(Ha00( @ mR,:(M`@@X~`@ @X~`(f@X~#%0XQXNu``Nu`Z0(HJ@gNS@g>S@g.S@gTM:(MaDp,:(]E`2avp,`ap,`ba^p,`a p,`JTM(g ap,`R?(1|aD1_p,2(tgpFpPpCpRtgJBgp/pFpPpSpRtgJBgp/pFpPpIpApRNuTM(g0(HJ@gS@gS@g`0(HJ@gbS@gBS@g ap,`:(baHMap,:(ErtgMIQI`:(Map,:(ME`:(Map,2(A`Hz*:(MEap,:(MNuHz :(ErtgMIQIaHp,:(MNuHzd:(MEa8p,:(MNuHzF2(Aap,:(MNutzgXpFpP0g(RBISEf<-pFpP0 Eg"RBISE Egg</`RBIQNuTM:(Ep#p$a&p,pFpP0(H0CMCPp p;pQNuPhi ???? ???? ???? ???? ???? ???? ???? ba9???? ???? ???? Log10(2)e Log2(e) Log10(e)0.0 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 1n(2) 1n(10) 10^0 10^1 10^2 10^4 10^8 10^16 10^32 10^64 10^128 10^256 10^512 10^1024 10^2048 10^4096 TM?((g TOap,`LaHp,TO1|bR pFpP0(HS@gS@gpC`pS`pIpApRNuTMalp,ap{:(MEa p}NuTMraDp,a0(@gp{p#p$0(@a@p}NuTMap{:(MEa p}r`TMa2(Agp{p#p$0ap}r`TMap,JFg BUFg @UFg XUFg ^UFg HUFg 6UFg JEg |SEg SEg SEg SEg `TMHy#~JFg UFg UFg UFg UFg UFg UFg JEg (SEg 4SEg 4SEg HSEg p`LTMNuTM` TM` TM:Ma p,`TM` TM(gJFg jUFg hUFg UFg UFg pUFg ^UFgbL BJEg SEg SEg SEg SEg `TM(f"pFpP0(rH0`pTM(gRHy#~JFgUFgUFg UFg UFgUFgUFg JEg &SEg 2SEg 2SEg FSEg n`JpFpP0(H0p,pFpP0(H0NuTM(gRHy$JFgbUFg`UFgxUFg~UFghUFgVUFg :JEg SEg SEg SEg SEg `pFpP0(H0p,pFpP0(H@0p,pFpP0(H0Nu:MEff2< 3 gRAp.RApWgpLp#p$ ` 0B,jP` :M8(B,jPgn`n8(g8b/8p-p(:MEaPp)p,p-p(:( MEa2p)`:MEap,:( MEa p,p#p$0B,jP` Hy%jTMJFgYFgUFgUFgUFgUFg JEg &SEg 2SEg 2SEg FSEg `Jp,8( g:Eap::]Ea~B,jPNuTM8( g\DaZp,Hy%YFgtUFgzUFgdUFgRUFg 6JEg SEg `8( fp,\DB,jP`B,jPTM8fa p,8(\Da8gp,8(DgSDgSDgSDg`SDgfSDgtSDgSDgSDg8(DDgBSDgJSDgfSDg*SDgSDgbv"SDgSDgSDgp?NupTpCNupIpTpTp0NupIpTpTp1NupD`pD`pBpUpSpCpRNupC`pVpApLNupSpCpCNupBpApD` pBpApC0(H0NupPpCpSpRNupPpSpRNupMpMpUpSpRNupD`pC` pU`pSpRpPNupPpCpRNupI` pM`pUpSpPNupVpBpRNupS`pDpFpCNupCpApApRNupCpApCpRNuHy(\TMJFgYFgUFgUFgUFgUFgJEg4SEg@SEg@SEgTSEg`Xp,8(:Eap::]EaB,bWo0jPNuHy(TMJFg~YFgUFgUFgUFgxUFg\JEgSEgSEgSEgSEgp`:8(p,\DB,jP` :(Eap::-Ea p,:(MEap::-MEap,p(8(\Dap)p:p(8-\Dap)XMB,jPNu:(Eap,:(MEap,Hy)<(:MYFgUFgUFgUFgvTMUFaXUMNuTMB,jPNup#0(ap, Ff aXTMB,jPNu F f&Up$0-ap(:Map)\MB,jPNuTMaB,jPNup#0B,jP``:(]EaNuJFgUFgUFglUFgUFgUFgHUFgNJEg$b0#4SEg*SEgSEg`nYg( +Jf |m0HN&Lw|m0Nup$0`2fp(JjDp-p$0`UM)MnTMJgTp(p[8\D DoRm?R[R=RJyJJJ-JJ;JJ1JJ0JJ9Jb ,JK K K KK#eK%K*K0K5KMKRKTKX*KbKhKZK`(KjKoKqKx'KzKKK8KK+KKKK)KK K7K?KAKKKKK?KK%KKKb $ >KK$KLLL LOLLPL L'QL)L0VL2L9WL;LBdLDLKYLMLTZLVL][L_Lg\LiLtL}GLLHLLILL]LL^LL_LL`LLaLLbLLcb*LL6LLLLMM M:MTM[M]Mf,MhMl&MnMu@Mw M MMSMMMMMSSgShSiT jT5kT^lTb bmTnToUpJyJJJ-JJ;JJ1JJ0JJ9JJK K K KK#eRRRRRRR RR!RRRRbDSnSy#RSSOSSPSS#QS%S0S9GS;SBHSDSKISXSbSSdSlTSMSVUS{JyJJJ-JJ;JJ1JJ0bJJ9JJK K K MMMNN$N N%N/N@eNN#WN%N-dNBNL*NNNZN\NfNhNrNtGNvNxHNzN|IN~NJNNKNNLNNMNNb:NNNFNNzNN6NNNNqNNNrNNsNNtNNuNNvNOwOOxOOyO O.OO#O%O2,O4OB/OCProjectProject info =POld b OReadEnvironment RESource RBinary RBObject ROWriteEnvironment WESource +Mark WSource -Mark WNBinary WBObject WOLink WLPreferences WPInsert IUpdate Source U Project UAZap Auto-Alloc ZAZap File ZFZap Includes ZIZap Source ZSAdd WorkMem =MAbout #Quit/Restart !Quick Quit !!AssemblerAssembleAssembleAOptimizeOCheck only ACObject info = EditorECommandb %lineEDebuggerDMonitorMPreferences Environment[Assembler ]AGA Guide =EditBlockMarkbComment;Uncomment:CopycCutxPasteiPastevFillfUnMarkuLowercaselUppercaseLRotateyRegisterkWritewVertical FillnSearchSearchSForwardsReplaceReplaceRForwardrDelete LinedSet MarksMark 1 !Mark 2@Mark 3#Mark 4$Mark 5%Mark 6^Mark 7&Mark 8*Mark 9(Mark 10)Jump MarksJump 1 1Jump 22Jump 33Jump 44Jump 55Jump 66Jump 77JumbXC:p 88Jump 99Jump 100Jump ;;JJump LinejMoveBegin of Line shift leftEnd of Line - rightPage Up - upPage Down - downUp 100aDown 100zToptBottomTLeft Word alt leftRight Word alt rightMake Macro,Do MacromGrab WordgExit escDebugStep One (Down)Enter (Right)RunrStep NsRun untill hereuAnimateiSkip instructionkEdit RegsxEdit MemorymAdd WatchaDel Watch 1 2 3 4 5 6 7 8Zap Watch'sZbZap Con B.P'sGJump AddressJJump MarkfB.P. ConditionDel Conditionj ! @ # $ % ^ & *B.P. AddressBB.P. MarkbZap All B.P.zChange Dx/FPxcExit escCommandsEditorJump Top TJump Bottom BSearch LZap Line(s) ZLPrint Line(s) PExtend Labels ELMemoryEdit MDisassemble DHEX Dump HASCII NDisassembleLine @DAssemble @AHEX Line @HASCII Line @NBinary Line @BSearch Memory bybSFill Memory FCopy Memory CCompare Memory QCreate Sinus CSInsertDisAssembly IDHEX Dump IHASCII Dump INBinary Dump IBCreate Sinus ISAssembleAssemble AMemory @AOptimize AODebug ADSymbols =SParameters Set PSMonitorJump JGo GStep KStatus XZap BPS ZBDiskRead Sector RSRead Track RTWrite Sector WSWrite Track WTCalc. Checksum CCExtern EOutput >Calbӿfculate ?Calculate float [Custom Registers =RMonitorDisassembledHex DumphASCII DumpnBin DumpbJump AddressjLast AddresslSet MarksMark 1 !Mark 2@Mark 3#Jump MarksJump 1 1Jump 22Jump 33Save BinsSet Start,Set End.Quick JumpqExit escSourcesF1 : F2 : F3 : F4 : F5 : b!S F6 : F7 : F8 : F9 : F10: y5a aBlZb ,mf0#++aR)yRi)yRi)yQi)yQi`aN#,+aJf ,mfa`a Jfa Jf#Va(a pa aa r lZbgHNp2apNuIp yhvr(#hz Vg 9hz,xN"¹hzg/a `Nu yhv,l N#bJfgVgJ @"9gȲ,f8IaZ Vg( Vg"yV,l N#V`#V <Nu#W2 @ f$ yg,l N yg <,l N`F fa`6 @f ,mfa`a.` fa#VNua ANpAg"ht"i""iAUJfBAg"hl"i""iAJfBAg"hp"i""iAWJfBNuCYG. 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* B!QuGW 3 0 BERSGPdA bd*SEQ!Ad}2S)!!Sԧ`W A SA 1LSBC!^Po1LS~]@C!^=OR#e1LRpU=z409LS7F\1D2S=O2 oF~-BC!01LS([ B|?`2/B4Cd,)bߥ ",C@d4 >S7C bH1?`8B%mg{դcC ?/    ߺE6 b`B!.2MFFE+ README.infop,% %l[)D % d @ ??_H @E!H Mu]`ltiviewFORMICONFACE+-+IMAG  1/tPP3SoDPPcSSXA'BO5SSSG/PPcSS9q'BD_SPSSS5GGOe 5SSSS;'B'"O550 'trtGO?5553_G"r/PU5550 'tttt?550 'rwBGE_ SSSS50 'rBrt5SSS_#w TtU?I0 /G?5553_#+A,rpTwE^#w 'GP3S_c#+A,rp?##||pU55503##+q,|wS3"||pcSS502222Ss#22? ||w5022#"|S50r222?||||53G0b22# /|? ||#22?07?y/h1,|1"2222#UQ-|31,ߜ122#"1p2Vh,##/P222# a=22?506 `^28Fj)IVZunIMAG+@@@@}x@E0A1D2p0" 4&A1D2WPo A!!9~~ TAd@C!N@d" WAdp!S?LAc8b@d*R?>Y3 0 BGQTsh7 1a' A :U@A 2? * B!QuGW 3 0 BERSGPdA bd*SEQ!Ad}2S)!!Sԧ`W A SA 1LSBC!^Po1LS~]@C!^=OR#e1LRpU=z409LS7F\1D2S=O2 oF~-BC!01LS([ B|?`2/B4Cd,)bߥ ",C@d4 >S7C bH1?`8B%mg{դcC ?/    ߺE6 b`B!.2MF2jE+ ASM-One.Prefp+RS -L7 +NL +AA +RL -XR -PD -LF +PG +HP -AE +DB -IL +CB -.S -CW -LN +AI -L: +DA +SS +OA -UL +;C +PI -PL +PS -RR +AU +SM -FW +FP -OD +DC +UD -EP +LD +KX +MP +SO +RD -WF +RT !.ASM *sources: |AAA|000|FFF|48B| [CPU4 [MMU0 ^40120032|00000258|00000320 \\3000\v asmone\ &topaz.font _ 'E+READMEp4 ASM-One V1.49-RC2 (24-03-2008) This Release Candidate 2 (modern word for Beta version B-) of ASM-One V1.49 is, as the name suggests, still a work in progress. I haven't done much after the last Beta release. But one thing that was a problem in the last version (that it would not run fine with WinUAE when you selected a MC68000) should now have been fixed. It somehow never occured to me that some additions I made used data at an odd address. Sorry for that o¦ne... Other things that have been changed are the IO requests for some devices, making the Color wheel more OS friendly and maken ASM-One compatible with MorphOS (I still have to test it on AmigaOS 4). Things that are still to come are checking of (dis)assembly of all instructions and addressing modes and I was working on supporting more fonts than just 8x8 fonts. But that didn't workout to well so I need to dive into that again. I'm also planning to update the Highlighted Error op{|Ktion (currently only works for immediate operands). All in all, there is still a lot to do. And I hope this time I can do it in less time and finaly release the final V1.49 version (which has been long over due)... Anyways, I hope you enjoy this one. And please reports bugs if you encounter them !!!! Kind regards, Boushh of TFA Read History.txt for a more detailed description of what has changed. Copyright ********* Copyright Notice ---------------- ASM-One V1.49-RC2 isgN Copyright (C) 2008 by Boushh of TFA. Disclaimer ---------- ASM-One V1.49-RC2 is offered "as is", and the authors will not be held responsible for any damage resulting from mistakes contained within, though the best effort has been made to ensure that the program works fine. Distribution ------------ This is only Copyrighted in order to protect the integrity of ASM-One V1.49-RC2 and to ensure its free availability to all. You may put it in a disk collection without prior permission from the authors (like the Fred Fish's disks and CD-ROMed versions of Aminet). You may NOT distribute ASM-One as a commercial package !! You may freely and for free distribute it across any medium. There is no shareware registration fee since this is "freeware". About ----- ASM-One is being developed on an Amiga A4000/60/PPC with 160 Mb of memory and two 4 Gb Harddisks.  Q%E+ History.txtp<Bug fixes and enhancements since Revision 482 (ASM-One V1.48) Revision 488 ------------ - A 3.x Call was executed on a Kickstart 2.x system during startup - Data at an odd address crashed ASM-One during startup on a MC68000 based Amiga - Data related to new directory caches was at an odd address and crashed on a MC68000 based Amiga while using File functions - Memory Indirect Post Indexed Addressing Modes with the Address Register surpressed always assembled the index bN4register to A1 or D1. - Confirmed working on MorphOS - Colors where not written correctly to the Pref file. - WP didn't work anymore due to changes in Color write routine. - Menu's are now also blocked when you Restart ASM-One, and haven't choosen any memory allocation yet. - Trackdisk.device is now opened with a propper IORequest. - Timer.device is now opened with a propper IORequest. - Console.device is now opened with a propper IORequest. - Screen colors where read backwjZards from the Pref file... - Rastport was already used before it was propperly filled ? - Forgot a screenpointer when using a call that needed it !! - Finetuning of the new color routines. - Rewrote '=C' DLC and how colors are written to the Pref file. - Rewrote how ASM-One loads the colors form the Pref file. - Added setting the Colors, Pens and Drawmode after opening the Screen. - Rewrote initial allocation of Screen Data. Revision 487 ------------ - Rewrote VBR code. -` Removed obsolete Exception Handler code. - Rewrote Exception Handeling for the MC68010/20/30. - Added Exception Handeling for the MC68040 and MC68060. - NEG and NEGX mixed up .L and .B sizes when assembling. - Had misplaced 504 bytes of data.. - Modified ASM-One's own Exception Handlers. Revision 486 ------------ - ReqTools check modified (there was never a leak B-) - New AUTO directive code did NOT skip the operands in Pass 1. - Added much better error handeling for tra0ck.device related stuff. Unknown errors now have a number returned. You can look the number up in trackdisk.i. - Changed 'Show Assembly Time' to use new timer routines. - Changed the routine that showed the time in the editor (more OS Friendly, less code). Also, time is shown according to your local settings (thus AM/PM or 24 Hours). - Recoded the routines responsible for opening and closing the ReqTools.library. Also fixed some memory that was never returned to thevT system (8 Kb). - Finally was able to fully document the early startup code. - Rearranged early startup code, removed obsolete code and shortened branches. - If ASM-One was unable to lock the startup directory, ASM-One would crash on trying to DupLock() since the Exec base pointer would still be in A6, while the program expected the Dos base pointer. - Commenting the source in great detail. - Removed some lines of code that where not needed. - Added a name to ASM-One's Me4$ssage Port. - ASM-One may not have worked on a KS2.x machine lately. The KS3.x detection I build in for the RTG stuff could potentialy crash ASM-One if KS3.x was not available. Revision 486a ------------- - Commenting the source in great detail. - Using native Amiga screen modes, ASM-One crashed when jumping into the debugger when entering the debugger was the first thing you did after loading the source.. Revision 486 ------------ - Removed some old parser code. Reviesion 485 ------------ - Update didn't work correctly anymore. Fixed.. - Commands executed by the AUTO directive will no longer be put into the commandline diary. - Previously during an assembly, the maximum number of characters for ALL the AUTO directive TOGETHER was 256. Now ASM-One handles 256 AUTO directive, with 256 characters each.. Revision 484 ------------ - Current Directory was not always set correctly when Reading or Writing a source. Fixed now..... @P - When a file could not be opened, you always got two requesters saying this (and the second requester could contain total bogus info). Fixed.. - Show Errors (Amiga+E) jumped to the wrong line and didn't show the error in the menubar. Fixed now. - When CPU was set to PPC, ASM-One didn't understand DC, DCB and DR directive. Fixed.. - MOVE.W CCR,D7 was assembled as being MOVE.W D7,CCR.. Not anymore.. - With the command 'V /' you will now go up one directory.  y\- V command output was to wide for 640 width screen. - CC (Calculate Checksum) command didn't work anymore.. Fixed now. Also added IO errors. Revision 483 ------------ - Added 'SETR', for WOS compatibility. SETR works the same as EQUR, only you can define it multiple times: SETCPU PPC hello: setr vr16 a: vavgsw hello,vr10,vr20 hello: setr vr9 b: vavgsw hello,vr10,vr20 SETCPU 040 hello: setr a0 c: move.l hello,d0 hello: setr a1 d: move.l hello,d0 Note: SETCP h|U is only used to assemble the instructions in the example above. SETR is (just like EQUR/EQUC) not CPU dependant.. - When disassembling PPC code, unknown instructions only showed dc.l, now dc.l . - Added 'popgpr', for compatibility with WOS/PowerASM. (see 'pushgpr'). Note: popgpr and pushgpr work with the same operands as MOVEM for the 68k. - 'pushgpr' didn't understand the slash ('/'). Now it does B-) - Added 'pushgpr' as PPC directi ៉ve/internal MACRO, for compatibility with WOS/PowerASM. This directive/MACRO is used in the WOS examples but is not included in the WOS includes as a MACRO becose a MACRO could never substract registers, neither would it allow the 'rA-rB' notation used by pushgpr: pushgpr r14-r31 Note: Register r0 can not be stored with this instruction !!! - lwzu was disassembled as lhwu, and lwz was disassembled as lhw. Not anymore.. - Added FEQUR directive for WOS compatibili _>ty. Btw: FEQUR is the same as EQUC, thus it will also except other PPC registers B-) - EQUR now also accepts PPC registers, for WOS compatibility. - Commenting of the source wF  E+ASM-One_V1.49-RC2.infop?FB#<P) B#|+ UUU_/z.@]@/[XX]qt@9.UOood@</[gd@8"""$[j@8dU lld@8 loi ll@8 llVnndUUU8oododoUQX8pUT@@@22^@D@@!@i_@ @@@@@@@@@@@@@ @@@@@@@@HHG@@@'@@@@@@@@@@@@UUU@@@UU_@@@':@@@'X@ꪫ@UU@@@@@+UUUW ("q7"2Qѐ5 "2Q 2@ 2""" 20h4QP5P5 PUWU*2UUUP;(UUUUUT?UUUUUUUUB#͜???*v=@??wW M@.!^v-,M@.!wwv+M@'!@-M@!@-M@!@vv2)L@662 @674L@66 @66+L@772*@ @UUP\@j@@8|@UUwU|@J`@@@@?@@@@UUPD" AT@@8`@ x`@P A`@ @z`@ y @`B$$# EPP `@' @`@p @X`A@DPB UTP@@P@k@uUU@j@@*D @AADiT KPBDB*BRX@@D@BbZ@@DBQB(XBPB `XBA%K @ !X@UUUX@UUPYbUUT?ݔl FORMNICONFACE,,'IMAG p?O B$$$B@ T$$/To.GA /!A 0BAG!A!'5YYYY2A! 75___ YYS$ ???9/!G Xc5YYYY_P/ ?????0sP/ ?0 G5WuW~27BB'????0B1"G5WuWuWuWuWuWuS! $'?????0BBG5WuWuWuWuW217B!1$$sPS# $'?7BAC 3S!Td13 $t!tAJ 14W7RBBAJ̬̣"ACquABDDss!d$11EcgXSDc110Vx_Vp[e__pKUpkeuVb"@8S5veP_`_/5hS6voVc$/3[P_`_O@aA[{o_{oX +ҘjIRfVZ)^2IMAGf3'  -!4P27PUuuw_w/#~uuupy2?dwK2?uGJ2?VWG/#P oooo`GJ2?̈̈̈̏vWD/#P oooo`Dz2?̈etJ2?&o`@z2?̈̈̈̌e@*2?_!#Pnxe@*2?_!#PvTF/#WU VD!#RGeDj2b5WZooooobUFJ25uzhedj2b5WZooooaFJ2 .j5uznxedj2b5WZoFj25tvPV/ #TGOdf!#WDTt} -FdJgHj2"5JuJuDt}UtvH!#wTTtt} GtJdd24duIutttoFFGdi2#@GGG@fDdda)!#^2/4*뛙! 88OGUq$kh!!#_hFi2 88WO_@6C!!#GGpdt2?O0? ///qQaߺEbB!*>l G$ HceUTSRQPONMLKJIHGFEDCBA@?>=<;:9876543210/.-,+*)('&%$#"! E+REGSDATAp  H[~}|{zyxwvutsrqponmlkjihgfedcba`_^]\[ZYXWV   A=\  \Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ~ Bit Use ---- --------------------------------------------------------- ~ Unused List of registers ordered by address. These include all versions of the Amiga ChipSet, up to the AGA Chips Set. Symbols Used: & = Register used by DMA channel only. % = Register used by DMA channel usually, processors sometimes. + = Address register pair. Low word uses DB1-DB15, High word DB0-DB4. ^ = Address not writable by the cop k#rocessor unless COPCON bit 1 is set true h = New for HiRes chip set. p = New for IAA chip set. A = Agnus/Alice chip set. D = Denise/Lisa chip set. P = Paula chip. W = Write. R = Read. ER = Early read. This is a DMA transfer to RAM, from either the disk or from the blitter. Ram timing requires data to be on the bus earlier than microprocessor read cycles. These transfers are therefore initiated by Agnus timing, rather than a read address o  wn the register address bus (RGA). S = Strobe (Write address with no register bits). PTL,PTH = 20 bit pointer that addresses DMA data. Must be reloaded by a processor before use (Vertical blank for bit plane and sprite pointers. and prior to starting the blitter for blitter pointers). (old chips - 18 bits). LCL,LCH = 20 bit location (starting address) of DMAdata. Used to automatically restart pointers. such as the Coprocessor program   counter (during vertical blank), and the audio sample counter (whenever the audio lentgh count is finished), (Old chips - 18 bits). MOD = 15 bit Modulo. A number that is automatically added to the memory address at the end of each line to generate the address for the beginning of the next line. This allows the blitter (or the display window) to operate on (or display) a window of data that is smaller than the ac I+tual picture in memory. (memory map) Uses 15 bits, plus sign extended. NAME ADDR R/W CHIP(s) FUNCTION ---------------------------------------------------------------------------# BLTDDAT & ^ 000 ER A Blitter dest. early read (dummy address).# DMACONR ^ 002 R A P Dma control (and blitter status) read.# VPOSR ^ 004 R A Read vert most sig. bits (and frame flop.# VHPOSR ^ 006 R A Read vert and horiz po yAsition of beam.# DSKDATR & ^ 008 ER P Disk data early read (dummy address).# JOY0DAT ^ 00A R D Joystick-mouse 0 data (vert,horiz).# JOT1DAT ^ 00C R D Joystick-mouse 1 data (vert,horiz).# CLXDAT ^ 00E R D Collision data reg. (read and clear).# ADKCONR ^ 010 R P Audio,disk control register read.# POT0DAT ^ 012 R P Pot counter pair 0 data (vert,horiz).# POT1DAT ^ 014 R P Pot cou hlx5nter pair 1 data (vert,horiz).# POTINP ^ 016 R P Pot pin data read.# SERDATR ^ 018 R P Serial port data and status read.# DSKBYTR ^ 01A R P Disk data byte and status read.# INTENAR ^ 01C R P Interrupt enable bits read.# INTREQR ^ 01E R P Interrupt request bits read.# DSKPTH + ^ 020 W A Disk pointer (high 5 bits).# DSKPTL + ^ 022 W A Disk pointer (low 15 bits).# DSKLEN ^ vy 024 W P Disk lentgh.# DSKDAT & ^ 026 W P Disk DMA data write.# REFPTR & ^ 028 W A Refresh pointer.# VPOSW ^ 02A W A Write vert most sig. bits(and frame flop).# VHPOSW ^ 02C W A D Write vert and horiz pos of beam.# COPCON ^ 02E W A Coprocessor control reg (CDANG).# SERDAT ^ 030 W P Serial port data and stop bits write.# SERPER ^ 032 W P Serial port period and  Scontrol.# POTGO ^ 034 W P Pot count start,pot pin drive enable data.# JOYTEST ^ 036 W D Write to all 4 joystick-mouse counters at once.# STREQU & ^ 038 S D Strobe for horiz sync with VB and EQU.# STRVBL & ^ 03A S D Strobe for horiz sync with VB (vert blank).# STRHOR & ^ 03C S D P Strobe for horiz sync.# STRLONG & ^ 03E S D Strobe for identification of long  ǚ?c horizontal line.# BLTCON0 ^ 040 W A Blitter control reg 0.# BLTCON1 ^ 042 W A Blitter control reg 1.# BLTAFWM ^ 044 W A Blitter first word mask for source A.# BLTALWM ^ 046 W A Blitter last word mask for source A.# BLTCPTH + ^ 048 W A Blitter pointer to source C (high 5 bits).# BLTCPTL + ^ 04A W A Blitter pointer to source C (low 15 bits).# BLTBPTH + ^ 04C ̘V W A Blitter pointer to source B (high 5 bits).# BLTBPTL + ^ 04E W A Blitter pointer to source B (low 15 bits).# BLTAPTH + ^ 050 W A Blitter pointer to source A (high 5 bits).# BLTAPTL + ^ 052 W A Blitter pointer to source A (low 15 bits).# BLTDPTH + ^ 054 W A Blitter pointer to destn D (high 5 bits).# BLTDPTL + ^ 056 W A Blitter pointer to destn D (low 15 bits).# BLTSIZE ^ 058 W A Bli xtter start and size (win/width,height).# BLTCON0L h ^ 05A W A Blitter control 0 lower 8 bits (minterms).# BLTSIZV h ^ 05C W A Blitter V size (for 15 bit vert size).# BLTSIZH h ^ 05E W A Blitter H size & start (for 11 bit H size).# BLTCMOD ^ 060 W A Blitter modulo for source C.# BLTBMOD ^ 062 W A Blitter modulo for source B.# BLTAMOD ^ 064 W A Blitter modulo for source A.# BLTDMOD ^ 066 W A  Blitter modulo for destn D.# ^ 068# ^ 06A# ^ 06C# ^ 06E# BLTCDAT & ^ 070 W A Blitter source C data reg.# BLTBDAT & ^ 072 W A Blitter source B data reg.# BLTADAT & ^ 074 W A Blitter source A data reg.# ^ 076# SPRHDAT &h 078 W A Ext logic UHRES sprite pointer and data identifier.# (BPLHDAT) ^ 07A ???? ?????.# L "ISAID h ^ 07C R D Chip revision level for Denise/Lisa.# DSKSYNC ^ 07E W P Disk sync pattern reg for disk read.# COP1LCH + 080 W A Coprocessor first location reg (high 5 bits).# COP1LCL + 082 W A Coprocessor first location reg (low 15 bits).# COP2LCH + 084 W A Coprocessor second reg (high 5 bits).# COP2LCL + 086 W A Co uO?processor second reg (low 15 bits).# COPJMP1 088 S A Coprocessor restart at first location.# COPJMP2 08A S A Coprocessor restart at second location.# COPINS 08C W A Coprocessor inst fetch identify.# DIWSTRT 08E W A D Display window start (upper left vert-hor pos).# DIWSTOP 090 W A D Display window stop (lower right vert-hor pos e8).# DDFSTRT 092 W A Display bit plane data fetch start.hor pos.# DDFSTOP 094 W A Display bit plane data fetch stop.hor pos.# DMACON 096 W A P DMA control write (clear or set).# CLXCON 098 W D Collision control.# INTENA 09A W P Interrupt enable bits (clear or set bits).# INTREQ 09C W P Interrupt request bits (clear or set bits).# ADKCON 09E W P Audio,disk,UA gXMRT,control.# AUD0LCH + 0A0 W A Audio channel 0 location (high 5 bits).# AUD0LCL + 0A2 W A Audio channel 0 location (low 15 bits).# AUD0LEN 0A4 W P Audio channel 0 lentgh.# AUD0PER 0A6 W P Audio channel 0 period.# AUD0VOL 0A8 W P Audio channel 0 volume.# AUD0DAT & 0AA W P Audio channel 0 data.# 0AC# 0AE# AUD1LCH + 0B0 W A Audio channel 1 loc  z ation (high 5 bits).# AUD1LCL + 0B2 W A Audio channel 1 location (low 15 bits).# AUD1LEN 0B4 W P Audio channel 1 lentgh.# AUD1PER 0B6 W P Audio channel 1 period.# AUD1VOL 0B8 W P Audio channel 1 volume.# AUD1DAT & 0BA W P Audio channel 1 data.# 0BC# 0BE# AUD2LCH + 0C0 W A Audio channel 2 location (high 5 bits).# AUD2LCL + 0C2 W A Audio chan !UHRnel 2 location (low 15 bits).# AUD2LEN 0C4 W P Audio channel 2 lentgh.# AUD2PER 0C6 W P Audio channel 2 period.# AUD2VOL 0C8 W P Audio channel 2 volume.# AUD2DAT & 0CA W P Audio channel 2 data.# 0CC# 0CE# AUD3LCH + 0D0 W A Audio channel 3 location (high 5 bits).# AUD3LCL + 0D2 W A Audio channel 3 location (low 15 bits).# AUD3LEN 0D4 W P A "{rudio channel 3 lentgh.# AUD3PER 0D6 W P Audio channel 3 period.# AUD3VOL 0D8 W P Audio channel 3 volume.# AUD3DAT & 0DA W P Audio channel 3 data.# 0DC# 0DE# BPL1PTH + 0E0 W A Bit plane pointer 1 (high 5 bits).# BPL1PTL + 0E2 W A Bit plane pointer 1 (low 15 bits).# BPL2PTH + 0E4 W A Bit plane pointer 2 (high 5 bits).# BPL2PTL + 0E6 W A Bit pla #LUne pointer 2 (low 15 bits).# BPL3PTH + 0E8 W A Bit plane pointer 3 (high 5 bits).# BPL3PTL + 0EA W A Bit plane pointer 3 (low 15 bits).# BPL4PTH + 0EC W A Bit plane pointer 4 (high 5 bits).# BPL4PTL + 0EE W A Bit plane pointer 4 (low 15 bits).# BPL5PTH + 0F0 W A Bit plane pointer 5 (high 5 bits).# BPL5PTL + 0F2 W A Bit plane pointer 5 (low 15 bits).# BPL6PTH + 0F4 W A Bit p $\tlane pointer 6 (high 5 bits).# BPL6PTL + 0F6 W A Bit plane pointer 6 (low 15 bits).# BPL7PTH + 0F8 W A Bit plane pointer 7 (high 5 bits).# BPL7PTL + 0FA W A Bit plane pointer 7 (low 15 bits).# BPL8PTH + 0FC W A Bit plane pointer 8 (high 5 bits).# BPL8PTL + 0FE W A Bit plane pointer 8 (low 15 bits).# BPLCON0 100 W A D Bit plane control reg (misc control bits).# BPLCON1 102 W D  %Yd2? Bit plane control reg (scroll val PF1,PF2).# BPLCON2 104 W D Bit plane control reg (priority control).# BPLCON3 106 W D Bit plane control reg (enhanced features).# BPL1MOD 108 W A Bit plane modulo (odd planes,or activefetch lines if bitplane scan-doubling is enabled.# BPL2MOD 10A W A Bit plane modulo (even planes or inactive- fetch lines &p if bitplane scan-doubling is enabled.# BPLCON4 p 10C W D Bit plane control reg (bitplane and sprite- masks).# CLXCON2 p 10E W D Extended collision control reg.# BPL1DAT & 110 W D Bit plane 1 data (parallel to serial convert).# BPL2DAT & 112 W D Bit plane 2 data (parallel to serial  'J convert).# BPL3DAT & 114 W D Bit plane 3 data (parallel to serial convert).# BPL4DAT & 116 W D Bit plane 4 data (parallel to serial convert).# BPL5DAT & 118 W D Bit plane 5 data (parallel to serial convert).# BPL6DAT & 11A W D Bit plane 6 data (parallel to serial convert). (Qr# BPL7DAT &p 11C W D Bit plane 7 data (parallel to serial convert).# BPL8DAT &p 11E W D Bit plane 8 data (parallel to serial convert).# SPR0PTH + 120 W A Sprite 0 pointer (high 5 bits).# SPR0PTL + 122 W A Sprite 0 pointer (low 15 bits).# SPR1PTH + 124 W A Sprite 1 pointer (high 5 bits).# SPR1PTL + 126 W A Sprite 1 pointe )glRr (low 15 bits).# SPR2PTH + 128 W A Sprite 2 pointer (high 5 bits).# SPR2PTL + 12A W A Sprite 2 pointer (low 15 bits).# SPR3PTH + 12C W A Sprite 3 pointer (high 5 bits).# SPR3PTL + 12E W A Sprite 3 pointer (low 15 bits).# SPR4PTH + 130 W A Sprite 4 pointer (high 5 bits).# SPR4PTL + 132 W A Sprite 4 pointer (low 15 bits).# SPR5PTH + 134 W A Sprite 5 pointer (high 5 bits).# S *HN5PR5PTL + 136 W A Sprite 5 pointer (low 15 bits).# SPR6PTH + 138 W A Sprite 6 pointer (high 5 bits).# SPR6PTL + 13A W A Sprite 6 pointer (low 15 bits).# SPR7PTH + 13C W A Sprite 7 pointer (high 5 bits).# SPR7PTL + 13E W A Sprite 7 pointer (low 15 bits).# SPR0POS % 140 W A D Sprite 0 vert-horiz start pos data.# SPR0CTL % 142 W A D Sprite 0 position and control data.# SPR0DATA %  +5 144 W D Sprite 0 image data register A.# SPR0DATB % 146 W D Sprite 0 image data register B.# SPR1POS % 148 W A D Sprite 1 vert-horiz start pos data.# SPR1CTL % 14A W A D Sprite 1 position and control data.# SPR1DATA % 14C W D Sprite 1 image data register A.# SPR1DATB % 14E W D Sprite 1 image data register B.# SPR2POS % 150 W A D Sprite 2 vert-horiz start pos data.# SPR2CTL % 152  ,d> W A D Sprite 2 position and control data.# SPR2DATA % 154 W D Sprite 2 image data register A.# SPR2DATB % 156 W D Sprite 2 image data register B.# SPR3POS % 158 W A D Sprite 3 vert-horiz start pos data.# SPR3CTL % 15A W A D Sprite 3 position and control data.# SPR3DATA % 15C W D Sprite 3 image data register A.# SPR3DATB % 15E W D Sprite 3 image data register B.# SPR4POS % 160 W A  -fD Sprite 4 vert-horiz start pos data.# SPR4CTL % 162 W A D Sprite 4 position and control data.# SPR4DATA % 164 W D Sprite 4 image data register A.# SPR4DATB % 166 W D Sprite 4 image data register B.# SPR5POS % 168 W A D Sprite 5 vert-horiz start pos data.# SPR5CTL % 16A W A D Sprite 5 position and control data.# SPR5DATA % 16C W D Sprite 5 image data register A.# SPR5DATB % 16E W D  .Vp Sprite 5 image data register B.# SPR6POS % 170 W A D Sprite 6 vert-horiz start pos data.# SPR6CTL % 172 W A D Sprite 6 position and control data.# SPR6DATA % 174 W D Sprite 6 image data register A.# SPR6DATB % 176 W D Sprite 6 image data register B.# SPR7POS % 178 W A D Sprite 7 vert-horiz start pos data.# SPR7CTL % 17A W A D Sprite 7 position and control data.# SPR7DATA % 17C W D  !/#R% Sprite 7 image data register A.# SPR7DATB % 17E W D Sprite 7 image data register B.# COLOR00 180 W D Color table 00.# COLOR01 182 W D Color table 01.# COLOR02 184 W D Color table 02.# COLOR03 186 W D Color table 03.# COLOR04 188 W D Color table 04.# COLOR05 18A W D Color table 05.# COLOR06 18C W D Color table 06.# COLOR07 18E W D  "0̹C Color table 07.# COLOR08 190 W D Color table 08.# COLOR09 192 W D Color table 09.# COLOR10 194 W D Color table 10.# COLOR11 196 W D Color table 11.# COLOR12 198 W D Color table 12.# COLOR13 19A W D Color table 13.# COLOR14 19C W D Color table 14.# COLOR15 19E W D Color table 15.# COLOR16 1A0 W D Color table 16.# COLOR17 #1r4)AT word is used for P15-P0 of AUDxPER. This alternating sequence is repeated. ~ 0A0/0A2/0B0/0B2/0C0/0C2/0D0/0D2 AUDxLCH - Audio Channel x Location (high 5 bits) AUDxLCL - Audio Channel x Location (low 15 bits) This pair of registers contains the 20 bit starting address(location) of audio channel x (x=0,1,2,3) DMA data. This is not a pointer reg and therfore only needs to be reloaded if a diffrent memory location is to be outputted. ~ 0 1?d\6A4/0B4/0C4/0D4 AUDxLEN - Audio Channel x Length This register contains the length (number of words) of audio channel x DMA data. ~ 0A6/0B6/0C6/0D6 AUDxPER - Audio Channel x Period This reg contains the period (rate) of audio channel x DMA data transfer. The minimum period is 124 clocks. This means that the smallest number that should be placed in this reg is 124. ~ 0A8/0B8/0C8/0D8 AUDxVOL - Audio Channel x Volume This reg co 2@.ntains the volume setting for audio channel x. Bits 6,5,4,3,2,1,0 specify 65 linear volume levels as shown below. +--------+--------------------------------------------------+ | BITS | USE | +--------+--------------------------------------------------+ | -15-07 | Not used | | 06 | Forces volume to max (64 ones,no zeros) |  3A | 05-00 | Sets one of the 64 levels (000000 = no output, | | | 111111 = 63 ones, one zero) | +--------+--------------------------------------------------+ ~ 0AA/0BA/0CA/0DA AUDxDAT - Audio Channel x Data This reg is the audio channel x (x=0,1,2,3) DMA data buffer. It contains 2 bytes of data (each byte is a twos complement signed integer) that are outputed sequentially (with digital to analog co 4Bnversion)to the audio output pins. With maximum volume, each byte can drive the audio outputs with 0.8 volts(peak to peak,typ). The audio DMA channel controller automatically transfers data to this reg from RAM. The processor can also write directly to this reg. When the DMA data is finished (words outputted=length) and the data in this reg has been used, an audio channel interrupt request is set. ~ 050/052/04C/04E/048/04A/054/0 5Cka56 BLTxPTH, BLTxPTL - Blitter Pointer to x (High 5 & Low 15 bits respectively). This pair of registers contains the 20 bit address of Blitter source (x=A,B,C) or dest. (x=D) DMA data. This pointer must be preloaded with the starting address of the data to be processed by te blitter. After the Blitter is finished, it will contain the last data address (plus increment and modulo). ~ 060/062/064/066 BLTxMOD - Blitter Modulo x  6D%IThis register contains the Modulo for Blitter source (x=A,B,C) or Dest (x=D). A modulo is a number that is automatically added to the address at the end of each line, in order that the address then points to the start of the next line. Each source or destination has it's own Modulo, allowing each to be different in size, while an identical area of each is used in the Blitter operation. ~ 044/046 BLTAFWM, BLYALWM - Blitter first and la 7E="st word mask for source A The patterns in the two registers are "anded" with the first and last words of each line of data from Source A into the Blitter. A zero in any bit overrides data from Source A. These registers should be set to all "ones" for fill mode or for line drawing mode. ~ 074/072/070 BLTxDAT - Blitter source x data register This register hold Source x (x=A,B,C) data for use by the Blitter. It is normally load 8Fr2ed by the Blitter DMA channel, however it may also be preloaded by the microprocessor. ~ 000 BLTDDAT - Blitter destination data register This register holds the data resulting from each word of Blitter operation until it is sent to a RAM destination. This is a dummy address and cannot be read by the microprocessor. The transfer is automatic during Blitter operation. ~ 040/05A/042 BLTCON0 - Blitter control register 0 BLTCON0L - Blitter 9G control register 0 (lower 8 bits) This is to speed up software - the upper bits are often the same. BLTCON1 - Blitter control register 1 These two control registers are used together to control blitter operations. There are 2 basic modes, are and line, which are selected by bit 0 of BLTCON1, as show below. +--------------------------+---------------------------+ | AREA MODE ("normal") | LINE MODE (line draw) |  :HZ +------+---------+---------+------+---------+----------+ | BIT# | BLTCON0 | BLTCON1 | BIT# | BLTCON0 | BLTCON1 | +------+---------+---------+------+---------+----------+ | 15 | ASH3 | BSH3 | 15 | ASH3 | BSH3 | | 14 | ASH2 | BSH2 | 14 | ASH2 | BSH2 | | 13 | ASH1 | BSH1 | 13 | ASH1 | BSH1 | | 12 | ASA0 | BSH0 | 12 | ASH0 | BSH0 | | 11 | USEA |  ;IT2]0 | 11 | 1 | 0 | | 10 | USEB | 0 | 10 | 0 | 0 | | 09 | USEC | 0 | 09 | 1 | 0 | | 08 | USED | 0 | 08 | 1 | 0 | | 07 | LF7 | DOFF | 07 | LF7 | DPFF | | 06 | LF6 | 0 | 06 | LF6 | SIGN | | 05 | LF5 | 0 | 05 | LF5 | OVF | | 04 | LF4 | EFE | 04 | LF4 | <J SUD | | 03 | LF3 | IFE | 03 | LF3 | SUL | | 02 | LF2 | FCI | 02 | LF2 | AUL | | 01 | LF1 | DESC | 01 | LF1 | SING | | 00 | LF0 | LINE(=0)| 00 | LF0 | LINE(=1) | +------+---------+---------+------+---------+----------+ ASH3-0 Shift value of A source BSH3-0 Shift value of B source and line texture USEA Mode control bit to use =KUE| source A USEB Mode control bit to use source B USEC Mode control bit to use source C USED Mode control bit to use destination D LF7-0 Logic function minterm select lines EFE Exclusive fill enable IFE Inclusive fill enable FCI Fill carry input DESC Descending (dec address)control bit LINE Line mode control bit SIGN Line draw sign flag  >LݐOVF Line/draw r/l word overflow flag SUD Line draw, Sometimes up or down (=AUD) SUL Line draw, Sometimes up or left AUL Line draw, Always up or left SING line draw, Single bit per horiz line DOFF Disables the D output- for external ALUs The cycle occurs normally, but the data bus is tristate (hires chips only) ~ 058 BLTSIZE - Blitter start and size (win/width, height) ?MhV This register contains the width and height of the blitter operation (in line mode width must = 2, height = line length). Writing to this register will start the Blitter, and should be done last, after all pointers and control registers have been initialized. BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 H9 H8 H7 H6 H5 H4 H3 H2 H1 H0 W5 W4 W3 W2 W1 W0 H=Height=Vertical lines (10 bits=1024 lines max)  @Nc W=Width=Horiz pixels (6 bits=64 words=1024 pixels max) ~ 05C BLTSIZV - Blitter V size (15 bit height) BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x h14 h13 h12 h11 h10 h9 h8 h7 h6 h5 h4 h3 h2 h1 h0 These are the blitter size regs for blits larger than the earlier chips could accept. The original commands are retained for compatibility. BLTSIZV should be written first, followed by BLTSIZH, which starts AO# the blitter. BLTSIZV need not be rewritten for subsequent bits if the vertical size is the same. Max size of blit 32k pixels * 32k lines, x's should be written to 0 for upward compatibility. ~ 05E BLTSIZH - Blitter H size & start (11 bit width) BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x x x x x w10 w9 w8 w7 w6 w5 w4 w3 w2 w1 w0 ~ 0E0/0E8/0EC/0F0/0F4/0F8/0FC BPLxPTH - Bit plane x pointer (high 5 bits)  BP˖݄ (x=1,2,3,4,5,6,7,8) ~ 0E2/0EA/0EE/0F2/0F6/0FA/0FE BPLxPTL - Bit plane pointer (low 15 bits) Address of bit plane x (x=1,2,3,4,5,6,7,8) DMA data. This pointer must be reinitialized by the processor or coprocessor to point in the beginning of bit plane date very vertical blank time. ~ 110/112/114/116/118/11A/11C/11E BPLxDAT - Bit plane x data (parallel to serial convert) These registers receive the DMA data fetched from RAM by the bit  CQynplane address pointers described above. They may also be rewritten by either micro. They act as an 8 word parallel to serial buffer for up to 8 memory 'bit planes'. x=1-8 the parallel to serial conversion ID triggered whenever bitplane #1 is written, indicing the completion of all bit planes for that word (16/32/64 pixels). The MSB is output first, and is therefore always on the left. ~ 108/10A BPL1MOD - Bit plane modulo (odd planes) BPL DRC2MOD - Bit Plane Modulo (even planes) These registers contain the modulos for the odd and even bit planes. A modulo is a number that is automaitcally added to the address at the end of each line, in order that the address then points to the start of the next line. Since they have seperate modulos, the odd and even bit planes may have sizes that are different from each other, as well as different from the display window size.  ES If scan-doubling is enabled, BPL1MOD serves as the primary bitplane modulos and BPL2MOD serves as the alternate. Lines whose LSBs of beam counter and DIWSTRT match are designated primary, whereas lines whose LSBs don`t match are designated alternate. ~ 100 BLTCON0 - Bit Plane Control Register 0 (misc, control bits) +------+---------+---------------------------------------------------------+ | BIT# | BPLCON0 | DESCRIPTION  FT+" | +------+---------+---------------------------------------------------------+ | 15 | HIRES | HIRES = High resoloution (640*200/640*400 interlace) | | | | mode | | 14 | BPU2 | Bit plane use code 0000-1000 (NODE thru 8 inclusive) | | 13 | BPU1 | | | 12 | BPU0 |  GU!/ | | 11 | HAM | Hold and modify mode, now using either 6 or 8 bit | | | | planes. | | 10 | DPF | Double playfield (PFI=odd FP2= even bit planes) | | | | now available in all resoloutions. | | | | (If BPU=6 and HAM=0 and DPF=0 a special mode is | | | | defined that allows bitplane 6 to cause an intensity | | |  HVBn | reduction of the other 5 bitplanes. The color | | | | register output selected by 5 bitplanes is shifted | | | | to half intensity by the 6th bit plane. This is | | | | called EXTRA-HALFBRITE Mode. | | 09 | COLOR | Enables color burst output signal | | 08 | GAUD | Genlock audio enable. This level appears on the ZD | | | | pin on denise dur IW&ing all blanking periods, unless ZDCLK | | | | bit is set. | | 07 | UHRES | Ultrahi res enables the UHRES pointers (for 1k*1k) (also| | | | needs bits in DMACON (hires chips only). | | | | Disables hard stops for vert, horiz display windows. | | 06 | SHRES | Super hi-res mode (35ns pixel width) | | 05 | BYPASS=0| Bitplanes are scrolled and prioritize JXE@d normally, but | | | | bypass color table and 8 bit wide data appear on R(7:0).| | 04 | BPU3=0 | See above (BPU0/1/2) | | 03 | LPEN | Light pen enable (reset on power up) | | 02 | LACE | Interlace enable (reset on power up) | | 01 | ERSY | External resync (HSYNC, VSYNC pads become inputs) | | | | (reset on power up) | KY5u | 00 | ECSENA=0| When low (default), the following bits in BPLCON3 are | | | | disabled: BRDRBLNK,BRDNTRAN,ZDCLKEN,BRDSPRT, and | | | | EXTBLKEN. These 5 bits can always be set by writing | | | | to BPLCON3, however there effects are inhibited until | | | | ECSENA goes high. This allows rapid context switching | | | | between pre-ECS viewports and new ones. | +------+---------+ LZY---------------------------------------------------------+ ~ 102 BPLCON1 - Bit Plane Control Register (horiz, scroll counter) +------+---------+---------------------------------------------------------+ | BIT# | BPLCON1 | DESCRIPTION | +------+---------+---------------------------------------------------------+ | 15 | PF2H7=0 | (PF2Hx =) Playfield 2 horizontal scroll code, x=0-7 | | 14 | PF2H6=0 |  M[״ | | 13 | PF2H1=0 | | | 12 | PF2H0=0 | | | 11 | PF1H7=0 | (PF1Hx =) Playfield 1 horizontal scroll code, x=0-7 | | 10 | PF1H6=0 | where PFyH0=LSB=35ns SHRES pixel (bits have been | | 09 | PF1H1=0 | renamed, old PFyH0 now PFyH2, ect). Now that the scroll | | 08 | PF1H0=0 | range has been quadrupled to allow for wider (32 N\0 or | | | | 64 bits) bitplanes. | | 07 | PF2H5 | | | 06 | PF2H4 | | | 05 | PF2H3 | | | 04 | PF2H2 | | | 03 | PF1H5 | | | 02 |  O]#PF1H4 | | | 01 | PF1H3 | | | 00 | PF1H2 | | +------+---------+---------------------------------------------------------+ ~ 104 BPLCON2 - Bit Plane Control Register (new control bits) +------+----------+--------------------------------------------------------+ | BIT# | BPLCON2 | DESCRIPTION  P^AL | +------+----------+--------------------------------------------------------+ | 15 | X | don`t care- but drive to 0 for upward compatibility! | | 14 | ZDBPSEL2 | 3 bit field which selects which bitplane is to be used | | | | for ZD when ZDBBPEN is set- 000 selects BB1 and 111 | | | | selects BP8. | | 13 | ZDBPSEL1 |  Q_ | | 12 | ZDBPSEL0 | | | 11 | ZDBPEN | Causes ZD pin to mirror bitplane selected by ZDBPSELx | | | | bits. This does not disable the ZD mode defined by | | | | ZDCTEN, but rather is "ored" with it. | | 10 | ZDCTEN | Causes ZD pin to mirror bit #15 of the active entry in | | | | high color table. When ZDCTEN is reset ZD reverts to | |  R`o3 | | mirroring color (0). | | 09 | KILLEHB | Disables extra half brite mode. | | 08 | RDRAM=0 | Causes color table address to read the color table | | | | instead of writing to it. | | 07 | SOGEN=0 | When set causes SOG output pin to go high | | 06 | PF2PRI | Gives playfield 2 priority over playfield 1. | | 05 | PF2P2 | Playf Sae)ield 2 priority code (with resp. to sprites). | | 04 | PF2P1 | | | 03 | PF2P0 | | | 02 | PF1P2 | Playfield 1 priority code (with resp. to sprites). | | 01 | PF1P1 | | | 00 | PF1P0 | | +------+----------+-------------------------- Tb]------------------------------+ ~ 106 BPLCON3 - Bit Plane Control Register (enhanced bits) +------+------------+--------------------------------------------------------+ | BIT# | BPLCON3 | DESCRIPTION | +------+------------+--------------------------------------------------------+ | | | | | 15 | BANK2=0 | BANKx = Selects one of eight color banks, x=0-2.  Uca2 | | 14 | BANK1=0 | | | 13 | BANK0=0 | | | 12 | PF2OF2=0 | Determine bit plane color table offset when playfield 2| | | | has priority in dual playfield mode: | | | +-----------+-------------------------------+------------+ | | | PF20F | AFFECTED BITPLANE | OFFSET | |  VdLE | +---+---+---+-------------------------------+------------+ | | | 2 | 1 | 0 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | (decimal) | | | +---+---+---+-------------------------------+------------+ | | | 0 | 0 | 0 | - | - | - | - | - | - | - | - | none | | | | 0 | 0 | 1 | - | - | - | - | - | - | 1 | - | 2 | | | | 0 | 1 | 0 | - | - | - | - | - | 1 | - | - | 4 | | |  Wep- | 0 | 1 | 1 | - | - | - | - | - | 1 | - | - | 8 (default)| | | | 1 | 0 | 0 | - | - | - | 1 | - | - | - | - | 16 | | | 1 | 0 | 1 | - | - | 1 | - | - | - | - | - | 32 | | | | 1 | 1 | 0 | - | 1 | - | - | - | - | - | - | 64 | | | | 1 | 1 | 1 | 1 | - | - | - | - | - | - | - | 128 | | | +---+---+---+---+---+---+---+---+---+---+---+------------+ | |  Xf. | | | 11 | PF2OF1=1 | | | 10 | PF2OF0=1 | | | 09 | LOCT=0 | Dictates that subsequent color palette values will be | | | | written to a second 12- bit color palette, constituting| | | | the RGB low minus order bits. Writes to the normal hi | | | | monu Ygۅs order color palette automattically copied to the | | | | low order for backwards compatibility. | | 08 | X | don`t care- but drive to 0 for upward compatibility! | | 07 | SPRES1=0 | Determine resolution of all 8 sprites (x=0,1): | | | | | | +-------+--------+---------------------------------------------+ | | |SPRES1 | SPRES0 | S Zh3hPRITE RESOLUTION | | | +-------+--------+---------------------------------------------+ | | |0 | 0 | ECS defaults (LORES,HIRES=140ns,SHRES=70ns) | | | |0 | 1 | LORES (140ns) | | | |1 | 0 | HIRES (70ns) | | | |1 | 1 | SHRES (35ns) | | | +-------+--------+---------- [i18-----------------------------------+ | | | | 06 | SPRES0=0 | | | 05 | BRDRBLNK=0 | "Border area" is blanked instead of color (0). | | | | Disabled when ECSENA low. | | 04 | BRDNTRAN=0 | "Border area" is non minus transparant (ZD pin is low | | | | when border is displayed). D \jUisabled when ECSENA low. | | 03 | X | don`t care- but drive to 0 for upward compatibility! | | 02 | ZDCLKEN=0 | ZD pin outputs a 14MHz clock whose falling edge | | | | coincides with hires (7MHz) video data. this bit when | | | | set disables all other ZD functions. | | | | Disabled when ESCENA low. | | 01 | BRDSPRT=0 | Enables sprites outside the display  ]kHYwindow. | | | | disabled when ESCENA low. | | 00 | EXTBLKEN=0 | Causes BLANK output to be programmable instead of | | | | reflecting internal fixed decodes. | | | | Disabled when ESCENA low. | +------+------------+--------------------------------------------------------+ ~ 10C BPLTCON4 - Bit Plane Control Register (display masks) +--- ^lx6---+----------+----------------------------------------------------------+ | BIT# | BPLCON4 | DESCRIPTION | +------+----------+----------------------------------------------------------+ | 15 | BPLAM7=0 | This 8 bit field is XOR`ed with the 8 bit plane color | | | | address, thereby altering the color address sent to the | | | | color table (x=1-8) | | 14 | BPL _m-}AM6=0 | | | 13 | BPLAM5=0 | | | 12 | BPLAM4=0 | | | 11 | BPLAM3=0 | | | 10 | BPLAM2=0 | | | 09 | BPLAM1=0 | | | 08 | BPLAM0=0 |  `n@T | | 07 | ESPRM7=0 | 4 Bit field provides the 4 high order color table address| | | | bits for even sprites: SPR0,SPR2,SPR4,SPR6. Default value| | | | is 0001 binary. (x=7-4) | | 06 | ESPRM6=0 | | | 05 | ESPRM5=0 | | | 04 | ESPRM4=1 |  aoT | | 03 | OSPRM7=0 | 4 Bit field provides the 4 high order color table address| | | | bits for odd sprites: SPR1,SPR3,SPR5,SPR7. Default value | | | | is 0001 binary. (x=7-4) | | 02 | OSPRM6=0 | | | 01 | OSPRM5=0 | | | 00 | OSPRM4=1 |  bp7 | +------+----------+----------------------------------------------------------+ ~ 098 CLxCON - Collision control This register controls which bitplanes are included (enabled) in collision detection, and their required state if included. It also controls the individual inclusion of odd numbered sprites in the collision detection, by logically ORing them with their correspond- ing even numbered  cqsprite. Writing to this register resets the bits in CLXCON2. +------+----------+-----------------------------------------------+ | BIT# | FUNCTION | DESCRIPTION | +------+----------+-----------------------------------------------+ | 15 | ENSP7 | Enable Sprite 7 (ORed with Sprite 6) | | 14 | ENSP5 | Enable Sprite 5 (ORed with Sprite 4) | | 13 | ENSP3 | Ena drhYble Sprite 3 (ORed with Sprite2) | | 12 | ENSP1 | Enable Sprite 1 (ORed with Sprite 0) | | 11 | ENSP6 | Enable bit plane 6 (match reqd. for collision | | 10 | ENSP5 | Enable bit plane 5 (match reqd. for collision | 09 ENSP4 Enable bit plane 4 (match reqd. for collision | 08 | ENSP3 | Enable bit plane 3 (match reqd. for collision | | 07 | ENSP2 | Enable bit plane 2 (match re esqd. for collision | | 06 | ENSP1 | Enable bit plane 1 (match reqd. for collision | | 05 | ENSP6 | Match value for bit plane 6 collision | | 04 | ENSP5 | Match value for bit plane 5 collision | | 03 | ENSP4 | Match value for bit plane 4 collision | | 02 | ENSP3 | Match value for bit plane 3 collision | | 01 | ENSP2 | Match value for bit plane 2 collision |  ft | 00 | ENSP1 | Match value for bit plane 1 collision | +------+----------+-----------------------------------------------+ ~ 10C CLXCON2 - Extended Collision Control This reg controls when bit planes 7 and 8 are included in collision detection, and there required state if included. Contents of this register are reset by a write to CLXCON. BITS INITIALIZED BY RESET +-------+----------+--------------------------- gueiwB--------------------+ | BIT# | FUNCTION | DESCRIPTION | +-------+----------+-----------------------------------------------+ | 15-08 | | unused | | 07 | ENBP8 | Enable bit plane 8 (match reqd. for | | | | collision) | | 06 | ENBP7 | Enable bit plane 7 (match reqd. for  hv5| | | | collision) | | 05-02 | | unused | | 01 | MVBP8 | Match value for bit plane 8 collision | | 00 | MVBP7 | Match value for bit plane 7 collision | +-------+----------+-----------------------------------------------+ Note: Disable bit planes cannot prevent collisions. Therefore if all bitplanes are iw disabled, collision will be continuous, regardless of the match values. ~ 00E CLXDAT - Collision detection register (read and clear) This address reads (and clears) the collision detection reg. The bit assignments are below Note: Playfield 1 is all odd numbered enabled bit planes. Playfield 2 is all even numbred enabled bit planes. +------+----------------------------------------+ | BIT# | COLLISIONS REGISTERED  jxl | +------+----------------------------------------+ | 15 | not used | | 14 | Sprite 4 (or 5) to Sprite 6 (or 7) | | 13 | Sprite 2 (or 3) to Sprite 6 (or 7) | | 12 | Sprite 2 (or 3) to Sprite 4 (or 5) | | 11 | Sprite 0 (or 1) to Sprite 6 (or 7) | | 10 | Sprite 0 (or 1) to Sprite 4 (or 5) | | 09 | Sprite 0 (or 1) to Sprite 2 (or 3) |  ky,2X} | 08 | Playfield 2 to Sprite 6 (or 7) | | 07 | Playfield 2 to Sprite 4 (or 5) | | 06 | Playfield 2 to Sprite 2 (or 3) | | 05 | Playfield 2 to Sprite 0 (or 1) | | 04 | Playfield 1 to Sprite 6 (or 7) | | 03 | Playfield 1 to Sprite 4 (or 5) | | 02 | Playfield 1 to Sprite 2 (or 3) | | 01 | Playfield 1 to Sprite 0 (or 1) | | 00 | Playfi lzۦeld 2 to Playfield 2 | +------+----------------------------------------+ ~ 180-1BE COLORxx - COLOR table xx There 32 of these registers (xx=00-31) and together with the banking bits they address the 256 locations in the color palette. There are actually two sets of color regs, selection of which is controlled by the LOCT reg bit. When LOCT = 0 the 4 MSB of red, green and blue video data are selected along with the  m{r0T bit for genlocks the low order set of registers is also selected as well, so that the 4 bits- values are automatically extended to 8 bits.This provides compatibility with old software. If the full range of palette values are desired, then LOCT can be set high and independant values for the 4 LSB of red, green and blue can be written. The low order color registers do not contain a transparency (T) bit. The table bel n|Oow shows the color register bit usage. +--------+-------------+-------------+-------------+-------------+ | BIT# | 15,14,13,12 | 11,10,09,08 | 07,06,05,04 | 03,02,01,00 | +--------+-------------+-------------+-------------+-------------+ | LOCT=0 | T X X X | R7 R6 R5 R4 | G7 G6 G5 G4 | B7 B6 B5 B4 | | LOCT=1 | X X X X | R3 R2 R1 R0 | G3 G2 G1 G0 | B3 B2 B1 B0 | +--------+-------------+-------------+-------------+------- o}Jq------+ T = TRANSPARENCY, R = RED, G = GREEN, B = BLUE, X = UNUSED T bit of COLOR00 thru COLOR31 sets ZD_pin HI, When that color is selected in all video modes. ~ 02E COPCON - Coprocessor control register This is a-1 bit register that when set true, allows the coprocessor to access the blitter hardware. This bit is cleared power on reset, so that the coprocessor cannot access the blitter hardware. +------+-------+-- p~Kql-----------------------------------------------+ | BIT# | NAME | FUNCTION | +------+-------+-------------------------------------------------+ | 01 | CDANG | Coprocessor danger mode. Allows coprocessor | | | | access to all RGA registers if true. | | | | (if 0, access to RGA>7E) | | | | (On old chips access to only RGA> q.:D3E if CDANG=1) | | | | (see VPOSR) | +------+-------+-------------------------------------------------+ ~ 088/08A COPJMP1 - Coprocessor restart at first location COPJMP2 - Coprocessor restart at second location These address are strobe address, that when written to cause the coprocessor to jump indirect useing the address contained in the first or second location regs described below. The  rY0coprocessor itself can write to these address, causeing it`s own jump indirect. ~ 080/082 COP1LCH - Coprocessor first location register (high 5 bits) (old-3 bits) COP1LCL - Coprocessor first location register (low 15 bits) These registers contain a jump address. See COPINS (08C) for a complete description. ~ 084/086 COP2LCH - Coprocessor second location register (high 5 bits) (old-3 bits) COP2LCL - Coprocessor second location register (low 15 bits)  sV These registers contain a jump address. See COPINS (08C) for a complete description. ~ 08C COPINS - Coprocessor instruction fetch identity. This is a dummy address that is generated by the coprocessor whenever it is loading instructions into its own instruction register. This actually occurs every coprocessor cycle except for the second (IR2) cycle of the MOVE instruction. The three types of instructions are shown below. t۷ MOVE: Move immediate to dest WAIT: Wait until beam counter is equal to, or greater than. (Keeps coprocessor off of bus until beam position has been reached) SKIP: Skip if beam counter is equal to, or greater than. (Skips following MOVE inst. unless beam position has been reached) +------------+-----------+-----------+ | MOVE | WAIT UNTIL| SKIP IF |  uz(h +------+-----+------+-----+-----+-----+-----+ | BIT# | IR1 | IR2 | IR1 | IR2 | IR1 | IR2 | +------+-----+------+-----+-----+-----+-----+ | 15 | x | RD15 | VP7 | BFD | VP7 | BFD | | 14 | x | RD14 | VP6 | VE6 | VP6 | VE6 | | 13 | x | RD13 | VP5 | VE5 | VP5 | VE5 | | 12 | x | RD12 | VP4 | VE4 | VP4 | VE4 | | 11 | x | RD11 | VP3 | VE3 | VP3 | VE3 | | 10 | x | RD10 | VP2 | VE2 | VP2 | V vIE2 | | 09 | x | RD09 | VP1 | VE1 | VP1 | VE1 | | 08 | DA8 | RD08 | VP0 | VE0 | VP0 | VE0 | | 07 | DA7 | RD07 | HP8 | HE8 | HP8 | HE8 | | 06 | DA6 | RD06 | HP7 | HE7 | HP7 | HE7 | | 05 | DA5 | RD05 | HP6 | HE6 | HP6 | HE6 | | 04 | DA4 | RD04 | HP5 | HE5 | HP5 | HE5 | | 03 | DA3 | RD03 | HP4 | HE4 | HP4 | HE4 | | 02 | DA2 | RD02 | HP3 | HE3 | HP3 | HE3 | | 01 | DA1 | RD01 | HP2 | HE2 |  w.HP2 | HE2 | | 00 | 0 | RD00 | 1 | 0 | 1 | 1 | +------+-----+------+-----+-----+-----+-----+ IR1=First instruction register IR2=Second insturction register DA =Destination address for MOVE instruction.Fetched during IR1 time,used during IR2 time on RGA bus. RD =RAM Data moved by MOVE instruction at IR2 time directly from RAM to the address given by the DA field. VP =Vertical beam posi xAݸtion comparison bit. HP =Horizontal beam position comparison bit. VE =Enable comparison (mask bit) HE =Enable comparison (mask bit) * Note: BFD = Blitter finished disable. When this bit is true, the blitter finished flag will have no effect on the coprocessor. When this bit is zero the blitter finished flag must be true (in addition to the rest of the bit comparisons) before the coprocessor can  yexit from it`s wait state, or skip over an instruction. Note that the V7 comparison cannot be masked. The coprocessor is basically a 2 cycle machine that requests the bus only during odd memory cycles. (4 memory cycles per in) It has priority over the blitter and micro. There are only three types of instructions, MOVE immediate, WAIT until ,and SKIP if. All instructions require 2 bus cycles (and two instruction  zvwords).Since only the odd bus cycles are requested, 4 memory cycle times are required per instruction. (memory cycles are 280 ns) There are two indirect jump registers COP1LC and COP2LC. These are 20 bit pointer registers whose contents are used to modify program counter for initalization or jumps. They are transfered to the program counter whenever strobe address COPJMP1 or COPJMP2 are written.In addition COP1LC is au {BRHtomatically used at the beginning of each vertical blank time. It is important that one of the jump registers be initalized and it`s jump strobe address hit, after power up but before coprocessor DMA is initalized.T his insures a determined startup address, and state. ~ 08E/090 DIWSTRT - Display window start (upper left vert-hor pos) DIWSTOP - Display window stop (lower right vert-hor pos) These registers control the display window siz |,&6Le and position, by locating the upper left and lower right corners. BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 USE V7 V6 V5 V4 V3 V2 V1 V0 H9 H8 H7 H6 H5 H4 H3 H2 DIWSTRT is vertically restricted to the upper 2/3 of the display (V8=0),and horizontally restricted to the left 3/4 of the display (H8=0). Note: See DIWHIGH for exceptions ~ 092/094 DDFSTRT - Display data fetch start (hori }: z. position) DDFSTOP - Display data fetch stop (horiz. position) These registers control the horizontal timing of the beginning and end of the bit plane DMA timing display data fetch. The vertical bit plane DMA timing is identical to the display windows described above. The bit plane Modulos are dependent on the bit plane horizontal size, and on this data fetch window size. Register bit assignment -------------------- ~4--- BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 USE X X X X X X X X H8 H7 H6 H5 H4 H3 H2 X Note: X bits should always be driven with 0 to maintain upward compatability The tables below show the start and stop timing for different register contents DDFSTRT (Left edge of display data fetch) +------------------+----+----+----+----+----+ | PURPOSE | H8 | H7 | H Vk6 | H5 | H4 | +------------------+----+----+----+----+----+ | Extra wide (max) | 0 | 0 | 1 | 0 | 1 | | | | | | | | | wide | 0 | 0 | 1 | 1 | 0 | | | | | | | | | normal | 0 | 0 | 1 | 1 | 1 | | | | | | | | | narrow | 0 | 1 | 0 | 0 | 0 | +------------------+----+ ]6----+----+----+----+ DDFSTOP (Right edge of display data fetch) +------------------+----+----+----+----+----+ | PURPOSE | H8 | H7 | H6 | H5 | H4 | +------------------+----+----+----+----+----+ | narrow | 1 | 1 | 0 | 0 | 1 | | | | | | | | | normal | 1 | 1 | 0 | 1 | 0 | | | | | | | | | wide (max) | +Q 1 | 1 | 0 | 1 | 1 | +------------------+----+----+----+----+----+ Note that these numbers will vary with variable beam counter mode set: (The maxes and mins, that is) ~ 1E4 DIWHIGH - Display window upper bits for start, stop This is an added register for Hires chips, and allows larger start & stop ranges. If it is not written, the above (DIWSTRT,STOP) description holds. If this register is written, direct start & stop  5q positions anywhere on the screen. It doesn`t affect the UHRES pointers. BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 X X H10 H1 H0 V10 V9 V8 X X H10 H1 H0 V10 V9 V8 (stop) | (start) Take care (X) bits should always be written to 0 to maintain upwards compatibility. H1 and H0 values define 70ns amd 35ns increments respectively, and n mVJew LISA bits. Note: In all 3 display window registers, horizontal bit positions have been renamed to reflect HIRES pixel increments, e.g. what used to be called H0 is now referred to as H2. ~ 002/096 DMACONR - DMA Control (and blitter status) read DMACON - DMA Control write (clear or set) This register controls all of the DMA channels, and contains blitter DMA status bits. +------+----------+-------------------------------------- F}------+ | BIT# | FUNCTION | DESCRIPTION | +------+----------+--------------------------------------------+ | 15 | SET/CLR | Set/Clear control bit. Determines if bits | | | | written wit a 1 get set or cleared. | | | | Bits written witn a zero are unchanged. | | 14 | BBUSY | Blitter busy status bit (read only) | | 13 | BZERO | Blitter &. logic zero status bit. (read only) | | 12 | X | | | 11 | X | | | 10 | BLTPRI | Blitter DMA prioiry (over CPU micro) | | | | (also called "blitter nasty") | | | | (disables /BLS pin, preventing micro | | | | from stealing any bus cycles while |  Sp | | | blitter DMA is running) | | 09 | DMAEN | Enable all DMA below (also UHRES DMA) | | 08 | BPLEN | Bit plane DMA enable | | 07 | COPEN | Coprocessor DMA enable | | 06 | BLTEN | Blitter DMA enable | | 05 | SPREN | Sprite DMA enable | | 04 | DSKEN | Disk DMA enable  J | | 03 | AUD3EN | Audio chanel 3 DMA enable | | 02 | AUD2EN | Audio chanel 2 DMA enable | | 01 | AUD1EN | Audio chanel 1 DMA enable | | 00 | AUD0EN | Audio chanel 0 DMA enable | +------+----------+--------------------------------------------+ ~ 020/022 DSKPTH - Disk Pointer (high 5 bits) (old-3 bits) DSKPTL - Disk Pointer (low 15 bit }?tps) This pair of registers contains the 20 bit address of disk DMA data. These address registers must be initalized by the processor or coprocessor before disk DMA is enabled. ~ 024 DKSLEN - Disk length +------+----------+------------------------------------+ | BIT# | FUNCTION | DESCRIPTION | +------+----------+------------------------------------+ | 15 | DMAEN | Disk DMA enable   x | | 14 | WRITE | Disk write (RAM or disk) if 1 | | 13-0 | LENGTH | Length (# of words) of DMA data. | +------+----------+------------------------------------+ ~ 01A DKSBYTR - Disk data byte and status read This register is the Disk-Microrocessor data buffer. Data from the disk (in read mode) is leaded into this register one byte at a time, and bit 15 (DSKBYT) is set true. +-------+----------+------- [G,-------------------------------------------+ | BIT# | FUNCTION | DESCRIPTION | +-------+----------+--------------------------------------------------+ | 15 | DSKBYT | Disk byte ready (reset on read) | | 14 | DMAON | DMAEN (DSKLEN) & DMAEN (DMACON) & DSKEN (DMACON) | | 13 | DISKWRITE| Mirror of bit 14 (WRITE) in DSKLEN | | 12 | WORDEQUAL| This bit true  ݥonly while DSKSYNC register | | | | equals the data from disk | | 11-08 | 0 | Not used | | 07-00 | DATA | Disk byte data | +-------+----------+--------------------------------------------------+ ~ 008/026 DSKDATR - Disk DMA data read (early read dummy address) DKSDAT - Disk DMA data write This register is the di V{sk-DMA data buffer.It contains 2 bytes of data that are either sent to (write) or received from (read) the disk. The DMA controller automatically transfers data to or from this register and RAM, and when the DMA data is finished (length=0) it causes a disk block interrupt. See interrupts below. ~ 07E DSKSYNC - Disk sync register, the match code for disk read synchronization. See ADKCON bit 10. ~ 09C/01C INTREQ - Interrupt request bits & (clear or set) INTREQR - Interrupt request bits (read) This register contains interrupt request bits (or flags). These bits may be polled by the processor, and if enabled by the bits listed in the next register, they may cause processor interrupts. Both a set and clear operation are required to load arbitary data into this register. The bit assignments are given below. +------+----------+-------+--------------------------- ְ-----------------+ | BIT# | FUNCTION | LEVEL | DESCRIPTION | +------+----------+-------+--------------------------------------------+ | 15 | SET/CLR | | Set/clear control bit. Determines if bits | | | | | written with a 1 get set or cleared. Bits | | | | | written with a zero are always unchanged. | | 14 | INTEN | | Master interrupt (enable only, no request) | | 13 | EXTER | 6  > | External interrupt | | 12 | DSKSYN | 5 | Disk sync register (DSKSYNC) matches disk | | 11 | RBF | 5 | Serial port receive buffer full | | 10 | AUD3 | 4 | Audio channel 3 block finished | | 09 | AUD2 | 4 | Audio channel 2 block finished | | 08 | AUD1 | 4 | Audio channel 1 block finished | | 07 | AUD0 | 4 | Audio channel 0 block finished  &+ | | 06 | BLIT | 3 | Blitter has finished | | 05 | VERTB | 3 | Start of vertical blank | | 04 | COPER | 3 | Coprocessor | | 03 | PORTS | 2 | I/O Ports and timers | | 02 | SOFT | 1 | Reserved for software initated interrupt. | | 01 | DSKBLK | 1 | Disk block finished | | 00 | TBE | 1 | Serial por Ht transmit buffer empty | +------+----------+-------+--------------------------------------------+ ~ 09A/01C INTENA - Interrupt enable bits (clear or set bits) INTENAR - Interrupt enable bits (read) This register contains interrupt enable bits. The bit assignment for both the request, and enable registers is given below. +------+----------+-------+--------------------------------------------+ | BIT# | FUNCTION | LEVEL | DESCRIPTION  I | +------+----------+-------+--------------------------------------------+ | 15 | SET/CLR | | Set/clear control bit. Determines if bits | | | | | written with a 1 get set or cleared. Bits | | | | | written with a zero are always unchanged. | | 14 | INTEN | | Master interrupt (enable only, no request) | | 13 | EXTER | 6 | External interrupt | | 12 | DSKSYN | 5   sz| Disk sync register (DSKSYNC) matches disk | | 11 | RBF | 5 | Serial port receive buffer full | | 10 | AUD3 | 4 | Audio channel 3 block finished | | 09 | AUD2 | 4 | Audio channel 2 block finished | | 08 | AUD1 | 4 | Audio channel 1 block finished | | 07 | AUD0 | 4 | Audio channel 0 block finished | | 06 | BLIT | 3 | Blitter has finished  8 | | 05 | VERTB | 3 | Start of vertical blank | | 04 | COPER | 3 | Coprocessor | | 03 | PORTS | 2 | I/O Ports and timers | | 02 | SOFT | 1 | Reserved for software initated interrupt. | | 01 | DSKBLK | 1 | Disk block finished | | 00 | TBE | 1 | Serial port transmit buffer empty | +------+----------+-------+------------- ꔩ-------------------------------+ ~ 00A/00C JOY0DAT - Joystick-mouse 0 data (left vert, horiz) JOY1DAT - Joystick-mouse 1 data (right vert, horiz) These addresses each read a 16 bit register. These in turn are loaded from the MDAT serial stream and are clocked in on the rising edge of SCLK. MLD output is used to parallel load the external parallel-to- serial converter.This in turn is loaded with the 4 quadrature inputs from each of two  qgame controller ports (8 total) plus 8 miscellaneous control bits which are new for LISA and can be read in upper 8 bits of LISAID. Register bits are as follows: Mouse counter usage (pins 1,3 =Yclock, pins 2,4 =Xclock) BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 JOY0DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 JOY1DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0  ٤ 0=LEFT CONTROLLER PAIR, 1=RIGHT CONTROLLER PAIR. (4 counters total).The bit usage for both left and right addresses is shown below. Each 6 bit counter (Y7-Y2,X7-X2) is clocked by 2 of the signals input from the mouse serial stream. Starting with first bit recived: +-------------------+-----------------------------------------+ | Serial | Bit Name | Description | +--------+--------- +@-+-----------------------------------------+ | 0 | M0H | JOY0DAT Horizontal Clock | | 1 | M0HQ | JOY0DAT Horizontal Clock (quadrature) | | 2 | M0V | JOY0DAT Vertical Clock | | 3 | M0VQ | JOY0DAT Vertical Clock (quadrature) | | 4 | M1V | JOY1DAT Horizontall Clock | | 5 | M1VQ | JOY1DAT Horizontall Clock (quadrature) |  L | 6 | M1V | JOY1DAT Vertical Clock | | 7 | M1VQ | JOY1DAT Vertical Clock (quadrature) | +--------+----------+-----------------------------------------+ Bits 1 and 0 of each counter (Y1-Y0,X1-X0) may be read to determine the state of the related input signal pair. This allows these pins to double as joystick switch inputs. Joystick switch closures can be deciphered as follows:  y +------------+------+---------------------------------+ | Directions | Pin# | Counter bits | +------------+------+---------------------------------+ | Forward | 1 | Y1 xor Y0 (BIT#09 xor BIT#08) | | Left | 3 | Y1 | | Back | 2 | X1 xor X0 (BIT#01 xor BIT#00) | | Right | 4 | X1 | +------------+------+----------- *----------------------+ ~ 036 JOYTEST - Write to all 4 joystick-mouse counters at once. Mouse counter write test data: BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 JOY0DAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx JOY1DAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx ~ 034 POTGO - Pot port (4 bit) bi-direction and data and pot counter start. ~ 016 POTINP - Pot pin data read  %V This register controls a 4 bit bi-direction I/O port that shares the same 4 pins as the 4 pot counters above. +-------+----------+---------------------------------------------+ | BIT# | FUNCTION | DESCRIPTION | +-------+----------+---------------------------------------------+ | 15 | OUTRY | Output enable for Paula pin 33 | | 14 | DATRY | I/O data Paula pin 33  H | | 13 | OUTRX | Output enable for Paula pin 32 | | 12 | DATRX | I/O data Paula pin 32 | | 11 | OUTLY | Out put enable for Paula pin 36 | | 10 | DATLY | I/O data Paula pin 36 | | 09 | OUTLX | Output enable for Paula pin 35 | | 08 | DATLX | I/O data Paula pin 35 | | 07- u401 | X | Not used | | 00 | START | Start pots (dump capacitors,start counters) | +-------+----------+---------------------------------------------+ ~ 028 REFPTR - Refresh pointer This register is used as a dynamic RAM refresh address generator. It's writeable for test purposes only, and should never be written by the microprocessor. ~ 030 SERDAT - Serial port data and stop bits write  -2 This address writes data to a transmit data buffer. Data from this buffer is moved into a serial shift register for output transmission whenever it is empty.This sets the interrupt request TBE (transmit buffer empty). A stop bit must be provided as part of the data word. The length of the data word is set by the position of the stop bit. BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 USE 0 0 0 i( 0 0 0 S D8 D7 D6 D5 D4 D3 D2 D1 D0 Note : S= Stop bit =1, D= data bits ~ 018 SERDATR - Serial port data and status read. This address reads data from a recive data buffer. Data in this buffer is loaded from a receiving shift register whenever it is full. Several interrupt request bits are also read at this address, along with the data as shown below. +------+----------+--------------------------------------------+ bH@ | BIT# | FUNCTION | DESCRIPTION | +------+----------+--------------------------------------------+ | 15 | OVRUN | Serial port receiver overun | | 14 | RBF | Serial port receive buffer full (mirror) | | 13 | TBE | Serial port transmit buffer empty (mirror) | | 12 | TSRE | Serial port transmit shift reg. empty | | 11 | RXD | RXD pin receiv  {pes UART serial data for | | | | direct bit test by the micro. | | 10 | X | Not used. | | 09 | STP | Stop bit | | 08 | STP-DB8 | Stop bit if LONG, data bit if not. | | 07 | DB7 | Data bit. | | 06 | DB6 | Data bit. | | 05 ' | DB5 | Data bit. | | 04 | DB4 | Data bit. | | 03 | DB3 | Data bit. | | 02 | DB2 | Data bit. | | 01 | DB1 | Data bit. | | 00 | DB0 | Data bit. | +------+----------+----------------------------- Ճ---------------+ ~ 032 SERPER - Serial port period and control This register contains the control bit LONG reffered to above, and a 15 bit number defining the serial port Baud rate. If this number is N,then the baud rate is 1 bit every (N+1)*.2794 microseconds. +-------+----------+------------------------------------------------+ | BIT# | FUNCTION | DESCRIPTION | +-------+----------+-------- 1c----------------------------------------+ | 15 | LONG | Defines serial receive as 9 bit word. | | 14-00 | RATE | Defines baud rate=1/((N+1)*.2794 microseconds) | +-------+----------+------------------------------------------------+ ~ 120/122 SPRxPTH - Sprite x pointer (high 5 bits) SPRxPTL - Sprite x pointer (low 15 bits) This pair of registers contains the address of sprite x DMA data. These address registers must  icbe initialized by the processor or Copper every vertical blank time. ~ SPRxPOS - Sprite x vert-horiz start position data. +-------+----------+------------------------------------------------+ | BIT# | SYM | FUNCTION | +-------+----------+------------------------------------------------+ | 15-08 | SV7-SV0 | Start vertical value.High bit (SV8) is | | | | in SPRxC H"TL register below. | | 07-00 | SH10-SH3 | Sprite horizontal start value. Low order | | | | 3 bits are in SPRxCTL register below. If | | | | SSCAN2 bit in FMODE is set, then disable | | | | SH10 horizontal coincidence detect.This bit | | | | is then free to be used by ALICE as an | | | | individual scan double '6 enable. | +-------+----------+------------------------------------------------+ ~ 142 SPRxCTL - Sprite position and control data +-------+----------+------------------------------------------------+ | BIT# | SYM | FUNCTION | +-------+----------+------------------------------------------------+ | 15-08 | EV7-EV0 | End (stop) vert. value. Low 8 bits | | 07  ͧs | ATT | Sprite attach control bit (odd sprites only) | | 06 | SV9 | Start vert value 10th bit. | | 05 | EV9 | End (stop) vert. value 10th bit | | 04 | SH1=0 | Start horiz. value, 70nS increment | | 03 | SH0=0 | Start horiz. value 35nS increment | | 02 | SV8 | Start vert. value 9th bit | | 01 | EV8 | E o(2nd (stop) vert. value 9th bit | | 00 | SH2 | Start horiz.value,140nS increment | +-------+----------+------------------------------------------------+ These 2 registers work together as position, size and feature sprite control registers.They are usually loaded by the sprite DMA channel, during horizontal blank, however they may be loaded by either processor any time. Writing to SPRxCTL disabl es the corresponding sprite. ~ 144/146 SPRxDATA - Sprite x image data register A SPRxDATB - Sprite x image data register B These registers buffer the sprite image data.They are usually loaded by the sprite DMA channel but may be loaded by either processor at any time. When a horizontal coincidence occurs the buffers are dumped into shift registers and serially outputed to the display, MSB first on the left. Note: Writing t bKXo the A buffer enables (arms) the sprite. Writing to the SPRxCTL registers disables the sprite. If enabled, data in the A and B buffers will be output whenever the beam counter equals the sprite horizontal position value in the SPRxPOS register. In lowres mode, 1 sprite pixel is 1 bitplane pixel wide.In HRES and SHRES mode, 1 sprite pixel is 2 bitplane pixels. The DATB bits are the 2SBs (worth 2) for the color registers,  bp and MSB for SHRES. DATA bits are LSBs of the pixels. ~ 038/03A/03C/03E STREQU - Strobe for horiz sync with VB (vert blank) and EQU STRVBL - Strobe for horiz sync with VB STRHOR - Strobe for horiz sync STRLONG - Strobe for identification of long horiz line (228CC) One of the first 3 strobe addresses above, it is placed on the RGA bus during the first refresh time slot of every other line, to identify lines with long counts (228- NTSC, HTOTAL+2- VA RBEAMEN=1 hires chips only).There are 4 refresh time slots and any not used for strobes will leave a null (1FE) address on the RGA bus. ~ 004/02A VPOSR - Read vert most sig. bits (and frame flop) VPOSW - Write most sig. bits (and frame flop) BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 USE LOF I6 I5 I4 I3 I2 I1 I0 LOL -- -- -- -- V10 V9 V8 LOF = Long frame(auto toggle control bit in BPLCON0) I0-I6 Chip ide Ԯpntitication: 8361 (Regular) or 8370 (Fat) (Agnus-ntsc) = 10 8367 (Pal) or 8371 (Fat-Pal) (Agnus-pal) = 00 8372 (Fat-hr) (agnushr),thru rev4 = 20 Pal, 30 NTSC 8372 (Fat-hr) (agnushr),rev 5 = 22 Pal, 31 NTSC 8374 (Alice) thru rev 2 = 22 Pal, 32 NTSC 8374 (Alice) rev 3 thru rev 4 = 23 Pal, 33 NTSC LOL = Long line bit. When low, it indicates short raster line. v9,1 |Vy0 -- hires chips only (20,30 identifiers) ~ 1DC BEAMCON0 - Beam Counter Control Bits +-------+----------------------------+ | BIT# | FUNCTION | +-------+----------------------------+ | 15 | (unused) | | 14 | HARDDIS | | 13 | LPENDIS | | 12 | VARVBEN | | 11 | LOLDIS |  q5 | 10 | CSCBEN | | 9 | VARVSYEN | | 8 | VARHSYEN | | 7 | VARBEAMEN | | 6 | DUAL | | 5 | PAL | | 4 | VARCSYEN | | 3 | (unused, formerly BLANKEN) | | 2 | CSYTRUE | | 1 | VSYTRUE |  *c | 0 | HSYTRUE | +-------+----------------------------+ HARDDIS = This bit is used to disable the hardwire vertical horizontal window limits. It is cleared upon reset. LPENDIS = When this bit is a low and LPE (BPLCON0,BIT 3) is enabled, the light-pen latched value(beam hit position) will be read by VHPOSR,VPOSR and HHPOSR. When the bit is a high the light-pen latched value is ignored and the actual beam coun ?`ter position is read by VHPOSR,VPOSR, and HHPOSR. VARVBEN = Use the comparator generated vertical blank (from VBSTRT,VBSTOP) to run the internal chip stuff-sending RGA signals to Denise, starting sprites,resetting light pen. It also disables the hard stop on the vertical display window. LOLDIS = Disable long line/short toggle. This is useful for DUAL mode where even multiples are wanted, or in any single display where th ݈is toggling is not desired. CSCBEN = The variable composite sync comes out on the HSY pin, and the variable conosite blank comes out on the VSY pin. The idea is to allow all the information to come out of the chip for a DUAL mode display. The normal monitor uses the normal composite sync, and the variable composite sync &blank come out the HSY & VSY pins. The bits VARVSTEN & VARHSYEN (below) have priority over this control 4c bit. VARVSYEN= Comparator VSY -> VSY pin. The variable VSY is set vertically on VSSTRT, reset vertically on VSSTOP, with the horizontal position for set set & reset HSSTRT on short fields (all fields are short if LACE = 0) and HCENTER on long fields (every other field if LACE = 1). VARHSYEN= Comparator HSY -> HSY pin. Set on HSSTRT value, reset on HSSTOP value. VARBEAMEN=Enables the variable beam counter comparators to operate  c5] (allowing diffrent beam counter total values) on the main horiz counter. It also disables hard display stops on both horizontal and vertical. DUAL = Run the horizontal comparators with the alternate horizontal beam counter, and starts the UHRES pointer chain with the reset of this counter rather than the normal one. This allows the UHRES pointers to come out more than once in a horizontal line, assuming there is s .Kome memory bandwidth left (it doesn`t work in 640*400*4 interlace mode) also, to keep the two displays synced, the horizontal line lentghs should be multiples of each other. If you are amazingly clever, you might not need to do this. PAL = Set appropriate decodes (in normal mode) for PAL. In variable beam counter mode this bit disables the long line/short line toggle- ends up short line. VARCSYEN= Enables CSY from the variable d  [ecoders to come out the CSY (VARCSY is set on HSSTRT match always, and also on HCENTER match when in vertical sync. It is reset on HSSTOP match when VSY and on both HBSTRT &HBSTOP matches during VSY. A reasonable composite can be generated by setting HCENTER half a horiz line from HSSTRT, and HBSTOP at (HSSTOP-HSSTRT) before HCENTER, with HBSTRT at (HSSTOP-HSSTRT) before HSSTRT. HSYTRUE, VSYTRUE, CSYTRUE = These change the  ǐPpolarity of the HSY*, VSY*, & CSY* pins to HSY, VSY, & CSY respectively for input and output. ~ 1E4 DIWHIGH - Display window upper bits for start, stop This is an added register for Hires chips, and allows larger start & stop ranges. If it is not written, the above (DIWSTRT,STOP) description holds. If this register is written, direct start & stop positions anywhere on the screen. It doesn`t affect the UHRES pointers.   BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 X X H10 H1 H0 V10 V9 V8 X X H10 H1 H0 V10 V9 V8 (stop) | (start) Take care (X) bits should always be written to 0 to maintain upwards compatibility. H1 and H0 values define 70ns amd 35ns increments respectively, and new LISA bits. Note: In all 3 display window registers, horizontal bit positi ons have been renamed to reflect HIRES pixel increments, e.g. what used to be called H0 is now referred to as H2. ~ 006/02C VHPOSR - Read vert and horiz position of beam, or lightpen VHPOSW - Write vert and horiz position of beam, or lightpen BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 USE V7 V6 V5 V4 V3 V2 V1 V0 H8 H7 H6 H5 H4 H3 H2 H1 Resolution = 1/160 of SCREEN WITH ( 280 nS) ~ 078 SPRHDAT - Ext. logic Ultra HiRes sprite pointer and data This identifies the cycle when this pointer address is on the bus accessing the memory. ~ 07C LISAID - Denise/Lisa (video out chip) revision level The original Denise (8362) does not have this register, so whatever value is left over on the bus from the last cycle will be there. ECS Denise (8373) returns hex (fc) in the lower 8 bits.Lisa returns hex (f8). The upper 8 bits of this Register are loa $.ded from the serial mouse bus, and are reserved for future hardware implentation. The 8 low-order bits are encoded as follows: +------+----------------------------------------------------------+ | BIT# | Description | +------+----------------------------------------------------------+ | 7-4 | Lisa/Denise/ECS Denise Revision level(decrement to | | | bump revision  Hlevel, hex F represents 0th rev. level). | | 3 | Maintain as a 1 for future generation | | 2 | When low indicates AA feature set (LISA) | | 1 | When low indicates ECS feature set (LISA or ECS DENISE) | | 0 | Maintain as a 1 for future generation | +------+----------------------------------------------------------+ ~ 1C0 HTOTAL - Highest colour clock count in horiz line  " BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x x x x x x x x h8 h7 h6 h5 h4 h3 h2 h1 (x`s should be driven to 0 for upward compatibility) Horiz line has theis many + 1 280nS increments. If the pal bit & LOLDIS are not high, long line/skort line toggle will occur, and there will be this many +2 every other line. Active if VARBEAMEN=1 or DUAL+1. ~ 1C2 HHSTOP - Horiz.  pg%line position for SYNC stop Sets # of colour clocks for sync stop (HTOTAL for bits) ~ 1C6/1C4 HBSTOP - Horizontal STOP position HBSTRT - Horizontal START position Bits 7-0 contain the stop and start positions, respectively, for programed horizontal blanking in 280nS increments.Bits 10-8 provide a fine position control in 35nS increments. +-------+----------+--------------+ | BIT# | FUNCTION | DESCRIPTION | +------ Md-+----------+--------------+ | 15-11 | x | (unused) | | 10 | H1 | 140nS | | 09 | H1 | 70nS | | 08 | H0 | 35nS | | 07 | H10 | 35840nS | | 06 | H9 | 17920nS | | 05 | H8 | 8960nS | | 04 | H7 | 4480nS | | 03 | H6 | 2240nS | | 02 | H5 | 1120nS |  вs| 01 | H4 | 560nS | | 00 | H3 | 280nS | +-------+----------+--------------+ ~ 1CA/1C8 VSSTOP - Vert position for VSYNC start VTOTAL - Highest numbered vertical line (VERBEAMEN = 1) It`s the line number to reset the counter, so there`s this many + 1 in a field. The exception is if the LACE bit is set (BPLCON0), in which case every other field is this many + 2 and the short field is this many + 1. ˷ ~ 1CE/1CC VBSTOP - Vertical line for VBLANK stop BNSRTR - Vertical line for VBLANK start (V10-0 <- D10-0) Affects CSY pin if BLAKEN=1 and VSY pin if CSCBEN=1 (see BEAMCON0) ~ 1DE HHSTRT - Horiz line position for HSYNC stop Set # of colour clocks for sync start (HTOTAL for bits) See BEAMCON0 for details of when these 2 are active. ~ 1E0 VSSTRT - Vertical sync start (VARVSY) ~ 1E2 HCENTER - Horizontal position (CCKs) of VSYNC on long field  %c This is necessary for interlace mode with variable beam counters. See BEAMCON0 for when it affects chip outputs. See HTOTAL for bits. ~ 1FC FMODE - Memory Fetch Mode. This register controls the fetch machanism for different types of Chip RAM accesses: +-------+----------+-------------------------------------------+ | BIT# | FUNCTION | DESCRIPTION | +-------+----------+----------- |[--------------------------------+ | 15 | SSCAN2 | Global enable for sprite scan-doubling. | | 14 | BSCAN2 | Enables the use of 2nd P/F modulus on an | | | | alternate line basis to support bitplane | | | | scan-doubling. | | 13-04 | Unused | | | 03 | SPAGEM | Sprite page mode (double CAS) | | M 02 | SPR32 | Sprite 32 bit wide mode | | 01 | BPAGEM | Bitplane Page Mode (double CAS) | | 00 | BLP32 | Bitplane 32 bit wide mode | +-------+----------+-------------------------------------------+ +------+-----+---------------+-----------+--------------+---------+ |BPAGEM|BPL32| Bitplane Fetch|Increment | Memory Cycle |Bus Width| +------+-----+---------------+-------- S---+--------------+---------+ | 0 | 0 | By 2 bytes |(as before)|normal CAS |16 | | 0 | 1 | By 4 bytes | |normal CAS |32 | | 1 | 0 | By 4 bytes | |double CAS |16 | | 1 | 1 | By 8 bytes | |double CAS |32 | +------+-----+---------------+-----------+--------------+---------+ +------+-----+------------+-----------+-------------+---------+ : |SPAGEM|SPR32|Sprite Fetch|Increment |Memory Cycle |Bus Width| +------+-----+------------+-----------+-------------+---------+ | 0 | 0 | By 2 bytes |(as before)| normal CAS | 16 | | 0 | 1 | By 4 bytes | | normal CAS | 32 | | 1 | 0 | By 4 bytes | | double CAS | 16 | | 1 | 1 | By 8 bytes | | double CAS | 32 | +------+-----+------------+-----------+- "nF------------+---------+ ~ 1FE NO-OP(NULL) - No Operation Can also indicate last 2 or 3 refresh cycles or the restart of the COPPER after lockup. ~ 1DA/1D8 HHPOSR - DUAL mode hires Hbeam counter read HHPOSW - DUAL mode hires Hbeam counter write This the secondary beam counter for the faster mode, triggering the UHRES pointers & doing the comparisons for HBSTRT,STOP,HTOTAL, HSSRT,HSSTOP (See HTOTAL for bits) ~ 07A/1E6 BLTHDAT  O|- Ext logic UHRES bit plane identifier BLTHMOD - Uhres bit plane modulo This is the number (sign extended) that is added to the UHRES bitplane pointer (BPLHPTL,H) every line, and then another 2 is added, just like the other modulos. ~ 1EC/1EE BPLHPTH - UHRES (VRAM) bit plane pntr (high 5 bits) BPLHPTL - UHRES (VRAM) bit plane pntr (low 15 bits) When UHRES is enabled, this pointer comes out on the 2nd 'free' cycle after the start of ea ch horizontal line. It`s modulo is added every time it comes out. 'free' means priority above the copper and below the fixed stuff (audio,sprites....). BPLHDAT comes out as an identifier on the RGA lines when the pointer address is valid so that external detectors can use this to do the special cycle for the VRAMs, The SHRHDAT gets the first and third free cycles. ~ 1D6 BPLHSTOP - UHRES bit plane vertical stop +-------+ ڽm\---------+ | BIT# | Name | +-------+---------+ | 15 | BPLHWRM | | 14-11 | Unused | | 10-0 | V10-V0 | +-------+---------+ BPLHWRM = Swaps the polarity of ARW* when the BPLHDAT comes out so that external devices can detect the RGA and put things into memory (ECS and later versions). ~ 1D4 BLTHSTRT - UHRES bit plane vertical stop This controls the line when the data fetch starts for t ahe BPLHPTH,L pointers. V10-V0 on DB10-0. ~ 012/014 POT0DAT - Pot counter data left pair (vert, horiz) POT1DAT - Pot counter data right pair (vert, horiz) These addresses each read a pair of 8 bit pot counters. (4 counters total). The bit assignment for both addresses is shown below. The counters are stopped by signals from 2 controller connectors (left-right) with 2 pins each. BIT# 15 14 13 12 11 10 09 08 07 06 05 04  ܢ7K 03 02 01 00 RIGHT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 LEFT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 +--------------------------+-------+ | CONNECTORS | PAULA | +-------+------+-----+-----+-------+ | Loc. | Dir. | Sym | pin | pin | +-------+------+-----+-----+-------+ | RIGHT | Y | RX | 9 | 33 | | RIGHT | X | RX | 5 | 32 |   0 | LEFT | Y | LY | 9 | 36 | | LEFT | X | LX | 5 | 35 | +-------+------+-----+-----+-------+ With normal (NTSC or PAL) horiz. line rate, the pots will give a full scale (FF) reading with about 500kohms in one frame time. With proportionally faster horiz line times, the counters will count proportionally faster. This should be noted when doing variable beam displays. ~ 1E8/1EA SPRHPTH - UHRES  ۇ sprite pointer (high 5 bits) SPRHPTL - UHRES sprite pointer (low 15 bits) This pointer is activated in the 1st and 3rd `free` cycles (see BPLHPTH,L) after horiz line start.It increments for the next line. ~ 1D2 SPRHSTOP - UHRES sprite vertical display stop BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SPRHWRM x x x x x v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 v0 SPRHWRM = Swaps the polarity of ARW*  _鬄when the SPRHDAT comes out so that external devices can detect the RGA and put things into memory. (ECS and later chips only) ~ 1D0 SPRHSTRT - UHRES sprite vertical display start BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x x x x x v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 v0 ~